This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG7dfc56c10746: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics. (authored by khchen).
Changed prior to commit: https://reviews.llvm.org/D125323?vs=428674&id=429171#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125323/new/ https://reviews.llvm.org/D125323 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
