pengfei added inline comments.
================
Comment at: llvm/test/CodeGen/X86/fpclamptosat_vec.ll:605
+; CHECK-NEXT: .cfi_def_cfa_offset 80
+; CHECK-NEXT: movss %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: movss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
----------------
pengfei wrote:
> pengfei wrote:
> > LuoYuanke wrote:
> > > Is the vector <4 x half> split to 4 scalar and pass by xmm? What's the
> > > ABI for vector half? Is there any case that test the scenario that run
> > > out of register and pass parameter through stack?
> > Good question! Previously, I discussed with GCC folks we won't support
> > vector in emulation. I expected the FE with pass whole vector through
> > stack. So a vector in IR is illegal to ABI and can be splited.
> > But seems GCC passes it by vector register. https://godbolt.org/z/a67rMhTW6
> > I'll double confirm with GCC folks.
> Discussed with GCC folks today. We should support the vector ABI. But we have
> to adding more patterns to support load/store etc. operations for vector
> type. I'd like to address this as a follow up.
Addressed by D127982.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107082/new/
https://reviews.llvm.org/D107082
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