olista01 updated this revision to Diff 64318.
https://reviews.llvm.org/D22292
Files:
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
Index: src/UnwindRegistersSave.S
===================================================================
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
@
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
- stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+ stm r0!, {r0-r7}
+ mov r1, r8
+ mov r2, r9
+ mov r3, r10
+ stm r0!, {r1-r3}
+ mov r1, r11
+ mov r2, r12
+ stm r0!, {r1-r2}
mov r2, sp
mov r3, lr
- str r2, [r0, #52]
- str r3, [r0, #56]
- str r3, [r0, #60] @ store return address as pc
+ str r2, [r0, #0]
+ str r3, [r0, #4]
+ str r3, [r0, #8] @ store return address as pc
+ @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+ @ It is safe to use here though because we are about to return, and cpsr is
+ @ not expected to be preserved.
+ movs r0, #0 @ return UNW_ESUCCESS
#else
@ 32bit thumb-2 restrictions for stm:
@ . the sp (r13) cannot be in the list
@ . the pc (r15) cannot be in the list in an STM instruction
stm r0, {r0-r12}
str sp, [r0, #52]
str lr, [r0, #56]
str lr, [r0, #60] @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
- @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
- @ It is safe to use here though because we are about to return, and cpsr is
- @ not expected to be preserved.
- movs r0, #0 @ return UNW_ESUCCESS
-#else
mov r0, #0 @ return UNW_ESUCCESS
#endif
JMP(lr)
Index: src/UnwindRegistersRestore.S
===================================================================
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,20 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
- ldr r2, [r0, #52]
- ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+ @ r8-r12: ldr into r1-r5, then mov to r8-r12
+ ldr r1, [r0, #0x20]
+ ldr r2, [r0, #0x24]
+ ldr r3, [r0, #0x28]
+ ldr r4, [r0, #0x2c]
+ ldr r5, [r0, #0x30]
+ mov r8, r1
+ mov r9, r2
+ mov r10, r3
+ mov r11, r4
+ mov r12, r5
+ ldr r2, [r0, #0x34]
+ ldr r3, [r0, #0x3c]
mov sp, r2
mov lr, r3 @ restore pc into lr
ldm r0, {r0-r7}
Index: src/UnwindRegistersSave.S
===================================================================
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
@
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
- stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+ stm r0!, {r0-r7}
+ mov r1, r8
+ mov r2, r9
+ mov r3, r10
+ stm r0!, {r1-r3}
+ mov r1, r11
+ mov r2, r12
+ stm r0!, {r1-r2}
mov r2, sp
mov r3, lr
- str r2, [r0, #52]
- str r3, [r0, #56]
- str r3, [r0, #60] @ store return address as pc
+ str r2, [r0, #0]
+ str r3, [r0, #4]
+ str r3, [r0, #8] @ store return address as pc
+ @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+ @ It is safe to use here though because we are about to return, and cpsr is
+ @ not expected to be preserved.
+ movs r0, #0 @ return UNW_ESUCCESS
#else
@ 32bit thumb-2 restrictions for stm:
@ . the sp (r13) cannot be in the list
@ . the pc (r15) cannot be in the list in an STM instruction
stm r0, {r0-r12}
str sp, [r0, #52]
str lr, [r0, #56]
str lr, [r0, #60] @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
- @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
- @ It is safe to use here though because we are about to return, and cpsr is
- @ not expected to be preserved.
- movs r0, #0 @ return UNW_ESUCCESS
-#else
mov r0, #0 @ return UNW_ESUCCESS
#endif
JMP(lr)
Index: src/UnwindRegistersRestore.S
===================================================================
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,20 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
- ldr r2, [r0, #52]
- ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+ @ r8-r12: ldr into r1-r5, then mov to r8-r12
+ ldr r1, [r0, #0x20]
+ ldr r2, [r0, #0x24]
+ ldr r3, [r0, #0x28]
+ ldr r4, [r0, #0x2c]
+ ldr r5, [r0, #0x30]
+ mov r8, r1
+ mov r9, r2
+ mov r10, r3
+ mov r11, r4
+ mov r12, r5
+ ldr r2, [r0, #0x34]
+ ldr r3, [r0, #0x3c]
mov sp, r2
mov lr, r3 @ restore pc into lr
ldm r0, {r0-r7}
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