This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4a29438f451: [RISCV][MC] Add minimal support for Ztso
extension (authored by reames).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133239/new/
https://reviews.llvm.org/D133239
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/elf-flags.s
Index: llvm/test/MC/RISCV/elf-flags.s
===================================================================
--- llvm/test/MC/RISCV/elf-flags.s
+++ llvm/test/MC/RISCV/elf-flags.s
@@ -5,6 +5,8 @@
# RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \
# RUN: | llvm-readobj --file-headers - \
# RUN: | FileCheck -check-prefix=CHECK-RVE %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
# CHECK-RVI: Flags [ (0x0)
# CHECK-RVI-NEXT: ]
@@ -17,4 +19,8 @@
# CHECK-RVE-NEXT: EF_RISCV_RVE (0x8)
# CHECK-RVE-NEXT: ]
+# CHECK-TSO: Flags [ (0x10)
+# CHECK-NEXT-TSO EF_RISCV_TSO (0x10)
+# CHECK-NEXT-TSO ]
+
nop
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -196,3 +196,6 @@
.attribute arch, "rv32izca0p70"
# CHECK: attribute 5, "rv32i2p0_zca0p70"
+
+.attribute arch, "rv32iztso0p1"
+# CHECK: attribute 5, "rv32i2p0_ztso0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -170,6 +171,7 @@
; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
bool HasStdExtZmmul = false;
+ bool HasStdExtZtso = false;
bool HasRV32 = false;
bool HasRV64 = false;
bool IsRV32E = false;
@@ -192,6 +193,7 @@
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
+ bool hasStdExtZtso() const { return HasStdExtZtso; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -454,6 +454,13 @@
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
+def FeatureStdExtZtso
+ : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
+ "'Ztso' (Memory Model - Total Store Order)">;
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
+ AssemblerPredicate<(all_of FeatureStdExtZtso),
+ "'Ztso' (Memory Model - Total Store Order)">;
+
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
// tuning CPU names.
def Feature32Bit
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -157,6 +157,8 @@
if (Features[RISCV::FeatureStdExtC])
EFlags |= ELF::EF_RISCV_RVC;
+ if (Features[RISCV::FeatureStdExtZtso])
+ EFlags |= ELF::EF_RISCV_TSO;
switch (ABI) {
case RISCVABI::ABI_ILP32:
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,6 +114,7 @@
{"zbt", RISCVExtensionVersion{0, 93}},
{"zca", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
+ {"ztso", RISCVExtensionVersion{0, 1}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -462,3 +462,11 @@
// RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
// CHECK-ZICBOP-EXT: __riscv_zicbop 1000000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iztso0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
+// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
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