zixuan-wu added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:106 + for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) + markSuperRegs(Reserved, Reg); + ---------------- I am wondering whether we need construct another new RegisterClass for RV32E instead of GPR, for example eGPR, so that the num and other info such as weight, etc of RegisterClass can adjust. Then the reserved logic is not necessary. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
