reames updated this revision to Diff 474782.
reames added a comment.
Address comments from @craig.topper
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137350/new/
https://reviews.llvm.org/D137350
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/XVentanaCondOps-valid.s
Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
@@ -157,6 +158,7 @@
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
bool HasStdExtZmmul = false;
bool HasStdExtZawrs = false;
bool HasStdExtZtso = false;
+ bool HasVendorXVentanaCondOps = false;
bool HasRV32 = false;
bool HasRV64 = false;
bool IsRV32E = false;
@@ -189,6 +190,7 @@
bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
bool hasStdExtZtso() const { return HasStdExtZtso; }
+ bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -0,0 +1,29 @@
+//===-- RISCVInstrInfoXVentana.td --------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Ventana Micro Systems.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XVentanaCondOps
+//===----------------------------------------------------------------------===//
+
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+ mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana" in
+class VTMaskedMove<bits<3> funct3, string opcodestr>
+ : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), opcodestr,
+ "$rd, $rs1, $rs2"> {
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1780,3 +1780,9 @@
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZicbo.td"
+
+//===----------------------------------------------------------------------===//
+// Vendor extensions
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrInfoXVentana.td"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,21 @@
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
+//===----------------------------------------------------------------------===//
+// Vendor extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureVendorXVentanaCondOps
+ : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
+ "'XVentanaCondOps' (Ventana Conditional Ops)">;
+def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
+ AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
+ "'XVentanaCondOps' (Ventana Conditional Ops)">;
+
+//===----------------------------------------------------------------------===//
+// LLVM specific features and extensions
+//===----------------------------------------------------------------------===//
+
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
// tuning CPU names.
def Feature32Bit
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -465,6 +465,16 @@
return Result;
}
}
+ if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) {
+ LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
+ Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
+ STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ }
+
LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Size = 4;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -104,6 +104,7 @@
{"svnapot", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
+ {"xventanacondops", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -149,14 +149,17 @@
Vendor Extensions
=================
-Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. At the moment, LLVM does not support any vendor extensions for RISC-V, but we expect this to change in the future.
-
-The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions.
+Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions.
Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation <https://clang.llvm.org/get_involved.html>`_.
It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions <https://github.com/riscv-non-isa/riscv-toolchain-conventions#conventions-for-vendor-extensions>`_. Exceptions to this naming will need to be strongly motivated.
+The current vendor extensions supported are:
+
+``XVentanaCondOps``
+ LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchai-convention document linked above. These instructions are only available for riscv64 at this time.
+
Specification Documents
=======================
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
// CHECK-NOT: __riscv_svinval
+// CHECK-NOT: __riscv_xventanacondops
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -432,3 +433,7 @@
// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}}
+
+// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
+// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
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