This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
stuij marked an inline comment as done.
Closed by commit rGcb261e30fbb1: [AArch64][clang] implement 2022 General
Data-Processing instructions (authored by stuij).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138488/new/
https://reviews.llvm.org/D138488
Files:
clang/test/Driver/aarch64-cssc.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
llvm/test/MC/AArch64/CSSC/abs_32.s
llvm/test/MC/AArch64/CSSC/abs_64.s
llvm/test/MC/AArch64/CSSC/cnt_32.s
llvm/test/MC/AArch64/CSSC/cnt_64.s
llvm/test/MC/AArch64/CSSC/ctz_32.s
llvm/test/MC/AArch64/CSSC/ctz_64.s
llvm/test/MC/AArch64/CSSC/smax_32_imm.s
llvm/test/MC/AArch64/CSSC/smax_32_reg.s
llvm/test/MC/AArch64/CSSC/smax_64_imm.s
llvm/test/MC/AArch64/CSSC/smax_64_reg.s
llvm/test/MC/AArch64/CSSC/smin_32_imm.s
llvm/test/MC/AArch64/CSSC/smin_32_reg.s
llvm/test/MC/AArch64/CSSC/smin_64_imm.s
llvm/test/MC/AArch64/CSSC/smin_64_reg.s
llvm/test/MC/AArch64/CSSC/umax_32_imm.s
llvm/test/MC/AArch64/CSSC/umax_32_reg.s
llvm/test/MC/AArch64/CSSC/umax_64_imm.s
llvm/test/MC/AArch64/CSSC/umax_64_reg.s
llvm/test/MC/AArch64/CSSC/umin_32_imm.s
llvm/test/MC/AArch64/CSSC/umin_32_reg.s
llvm/test/MC/AArch64/CSSC/umin_64_imm.s
llvm/test/MC/AArch64/CSSC/umin_64_reg.s
llvm/test/MC/AArch64/armv8.9a-cssc.s
llvm/test/MC/AArch64/rprfm.s
llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
llvm/unittests/Support/TargetParserTest.cpp
Index: llvm/unittests/Support/TargetParserTest.cpp
===================================================================
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
- AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16};
+ AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
std::vector<StringRef> Features;
@@ -1671,6 +1671,7 @@
EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
// Assuming we listed every extension above, this should produce the same
// result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK: abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK: abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK: cnt x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK: cnt w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK: ctz x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK: ctz w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK: smax x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK: smax x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK: smax w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x11]
+# CHECK: smax w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x9a]
+# CHECK: smin x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc8,0x91]
+# CHECK: smin x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x1a]
+# CHECK: smin w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc8,0x11]
+# CHECK: smin w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x64,0xc3,0x9a]
+# CHECK: umax x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc4,0x91]
+# CHECK: umax x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x64,0xc3,0x1a]
+# CHECK: umax w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc4,0x11]
+# CHECK: umax w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x6c,0xc3,0x9a]
+# CHECK: umin x1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xcc,0x91]
+# CHECK: umin x1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x6c,0xc3,0x1a]
+# CHECK: umin w1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xcc,0x11]
+# CHECK: umin w1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
Index: llvm/test/MC/AArch64/rprfm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/rprfm.s
@@ -0,0 +1,528 @@
+// RPRFM is now a v8.0a optional instruction, and overlaps with PRFM. This test
+// checks we can assemble as PRFM, and we always disassemble as RPRFM.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+rprfm #0, x0, [x0]
+// CHECK-INST: rprfm pldkeep, x0, [x0]
+// CHECK-ENCODING: [0x18,0x48,0xa0,0xf8]
+
+rprfm #1, x0, [x0]
+// CHECK-INST: rprfm pstkeep, x0, [x0]
+// CHECK-ENCODING: [0x19,0x48,0xa0,0xf8]
+
+rprfm #2, x0, [x0]
+// CHECK-INST: rprfm #2, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x48,0xa0,0xf8]
+
+rprfm #3, x0, [x0]
+// CHECK-INST: rprfm #3, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x48,0xa0,0xf8]
+
+rprfm #4, x0, [x0]
+// CHECK-INST: rprfm pldstrm, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x48,0xa0,0xf8]
+
+rprfm #5, x0, [x0]
+// CHECK-INST: rprfm pststrm, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x48,0xa0,0xf8]
+
+rprfm #6, x0, [x0]
+// CHECK-INST: rprfm #6, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x48,0xa0,0xf8]
+
+rprfm #7, x0, [x0]
+// CHECK-INST: rprfm #7, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x48,0xa0,0xf8]
+
+rprfm #8, x0, [x0]
+// CHECK-INST: rprfm #8, x0, [x0]
+// CHECK-ENCODING: [0x18,0x58,0xa0,0xf8]
+
+rprfm #9, x0, [x0]
+// CHECK-INST: rprfm #9, x0, [x0]
+// CHECK-ENCODING: [0x19,0x58,0xa0,0xf8]
+
+rprfm #10, x0, [x0]
+// CHECK-INST: rprfm #10, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x58,0xa0,0xf8]
+
+rprfm #11, x0, [x0]
+// CHECK-INST: rprfm #11, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x58,0xa0,0xf8]
+
+rprfm #12, x0, [x0]
+// CHECK-INST: rprfm #12, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x58,0xa0,0xf8]
+
+rprfm #13, x0, [x0]
+// CHECK-INST: rprfm #13, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x58,0xa0,0xf8]
+
+rprfm #14, x0, [x0]
+// CHECK-INST: rprfm #14, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x58,0xa0,0xf8]
+
+rprfm #15, x0, [x0]
+// CHECK-INST: rprfm #15, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x58,0xa0,0xf8]
+
+rprfm #16, x0, [x0]
+// CHECK-INST: rprfm #16, x0, [x0]
+// CHECK-ENCODING: [0x18,0x68,0xa0,0xf8]
+
+rprfm #17, x0, [x0]
+// CHECK-INST: rprfm #17, x0, [x0]
+// CHECK-ENCODING: [0x19,0x68,0xa0,0xf8]
+
+rprfm #18, x0, [x0]
+// CHECK-INST: rprfm #18, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x68,0xa0,0xf8]
+
+rprfm #19, x0, [x0]
+// CHECK-INST: rprfm #19, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x68,0xa0,0xf8]
+
+rprfm #20, x0, [x0]
+// CHECK-INST: rprfm #20, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x68,0xa0,0xf8]
+
+rprfm #21, x0, [x0]
+// CHECK-INST: rprfm #21, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x68,0xa0,0xf8]
+
+rprfm #22, x0, [x0]
+// CHECK-INST: rprfm #22, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x68,0xa0,0xf8]
+
+rprfm #23, x0, [x0]
+// CHECK-INST: rprfm #23, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x68,0xa0,0xf8]
+
+rprfm #24, x0, [x0]
+// CHECK-INST: rprfm #24, x0, [x0]
+// CHECK-ENCODING: [0x18,0x78,0xa0,0xf8]
+
+rprfm #25, x0, [x0]
+// CHECK-INST: rprfm #25, x0, [x0]
+// CHECK-ENCODING: [0x19,0x78,0xa0,0xf8]
+
+rprfm #26, x0, [x0]
+// CHECK-INST: rprfm #26, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x78,0xa0,0xf8]
+
+rprfm #27, x0, [x0]
+// CHECK-INST: rprfm #27, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x78,0xa0,0xf8]
+
+rprfm #28, x0, [x0]
+// CHECK-INST: rprfm #28, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x78,0xa0,0xf8]
+
+rprfm #29, x0, [x0]
+// CHECK-INST: rprfm #29, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x78,0xa0,0xf8]
+
+rprfm #30, x0, [x0]
+// CHECK-INST: rprfm #30, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x78,0xa0,0xf8]
+
+rprfm #31, x0, [x0]
+// CHECK-INST: rprfm #31, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x78,0xa0,0xf8]
+
+rprfm #32, x0, [x0]
+// CHECK-INST: rprfm #32, x0, [x0]
+// CHECK-ENCODING: [0x18,0xc8,0xa0,0xf8]
+
+rprfm #33, x0, [x0]
+// CHECK-INST: rprfm #33, x0, [x0]
+// CHECK-ENCODING: [0x19,0xc8,0xa0,0xf8]
+
+rprfm #34, x0, [x0]
+// CHECK-INST: rprfm #34, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xc8,0xa0,0xf8]
+
+rprfm #35, x0, [x0]
+// CHECK-INST: rprfm #35, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xc8,0xa0,0xf8]
+
+rprfm #36, x0, [x0]
+// CHECK-INST: rprfm #36, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xc8,0xa0,0xf8]
+
+rprfm #37, x0, [x0]
+// CHECK-INST: rprfm #37, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xc8,0xa0,0xf8]
+
+rprfm #38, x0, [x0]
+// CHECK-INST: rprfm #38, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xc8,0xa0,0xf8]
+
+rprfm #39, x0, [x0]
+// CHECK-INST: rprfm #39, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xc8,0xa0,0xf8]
+
+rprfm #40, x0, [x0]
+// CHECK-INST: rprfm #40, x0, [x0]
+// CHECK-ENCODING: [0x18,0xd8,0xa0,0xf8]
+
+rprfm #41, x0, [x0]
+// CHECK-INST: rprfm #41, x0, [x0]
+// CHECK-ENCODING: [0x19,0xd8,0xa0,0xf8]
+
+rprfm #42, x0, [x0]
+// CHECK-INST: rprfm #42, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xd8,0xa0,0xf8]
+
+rprfm #43, x0, [x0]
+// CHECK-INST: rprfm #43, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xd8,0xa0,0xf8]
+
+rprfm #44, x0, [x0]
+// CHECK-INST: rprfm #44, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xd8,0xa0,0xf8]
+
+rprfm #45, x0, [x0]
+// CHECK-INST: rprfm #45, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xd8,0xa0,0xf8]
+
+rprfm #46, x0, [x0]
+// CHECK-INST: rprfm #46, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xd8,0xa0,0xf8]
+
+rprfm #47, x0, [x0]
+// CHECK-INST: rprfm #47, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xd8,0xa0,0xf8]
+
+rprfm #48, x0, [x0]
+// CHECK-INST: rprfm #48, x0, [x0]
+// CHECK-ENCODING: [0x18,0xe8,0xa0,0xf8]
+
+rprfm #49, x0, [x0]
+// CHECK-INST: rprfm #49, x0, [x0]
+// CHECK-ENCODING: [0x19,0xe8,0xa0,0xf8]
+
+rprfm #50, x0, [x0]
+// CHECK-INST: rprfm #50, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xe8,0xa0,0xf8]
+
+rprfm #51, x0, [x0]
+// CHECK-INST: rprfm #51, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xe8,0xa0,0xf8]
+
+rprfm #52, x0, [x0]
+// CHECK-INST: rprfm #52, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xe8,0xa0,0xf8]
+
+rprfm #53, x0, [x0]
+// CHECK-INST: rprfm #53, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xe8,0xa0,0xf8]
+
+rprfm #54, x0, [x0]
+// CHECK-INST: rprfm #54, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xe8,0xa0,0xf8]
+
+rprfm #55, x0, [x0]
+// CHECK-INST: rprfm #55, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xe8,0xa0,0xf8]
+
+rprfm #56, x0, [x0]
+// CHECK-INST: rprfm #56, x0, [x0]
+// CHECK-ENCODING: [0x18,0xf8,0xa0,0xf8]
+
+rprfm #57, x0, [x0]
+// CHECK-INST: rprfm #57, x0, [x0]
+// CHECK-ENCODING: [0x19,0xf8,0xa0,0xf8]
+
+rprfm #58, x0, [x0]
+// CHECK-INST: rprfm #58, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xf8,0xa0,0xf8]
+
+rprfm #59, x0, [x0]
+// CHECK-INST: rprfm #59, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xf8,0xa0,0xf8]
+
+rprfm #60, x0, [x0]
+// CHECK-INST: rprfm #60, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xf8,0xa0,0xf8]
+
+rprfm #61, x0, [x0]
+// CHECK-INST: rprfm #61, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xf8,0xa0,0xf8]
+
+rprfm #62, x0, [x0]
+// CHECK-INST: rprfm #62, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xf8,0xa0,0xf8]
+
+rprfm #63, x0, [x0]
+// CHECK-INST: rprfm #63, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xf8,0xa0,0xf8]
+
+// Aliases
+// -----------------------------------------------------------------------------
+
+prfm #24, [x0, w0, uxtw]
+// CHECK-INST: rprfm pldkeep, x0, [x0]
+// CHECK-ENCODING: [0x18,0x48,0xa0,0xf8]
+
+prfm #25, [x0, w0, uxtw]
+// CHECK-INST: rprfm pstkeep, x0, [x0]
+// CHECK-ENCODING: [0x19,0x48,0xa0,0xf8]
+
+prfm #26, [x0, w0, uxtw]
+// CHECK-INST: rprfm #2, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x48,0xa0,0xf8]
+
+prfm #27, [x0, w0, uxtw]
+// CHECK-INST: rprfm #3, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x48,0xa0,0xf8]
+
+prfm #28, [x0, w0, uxtw]
+// CHECK-INST: rprfm pldstrm, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x48,0xa0,0xf8]
+
+prfm #29, [x0, w0, uxtw]
+// CHECK-INST: rprfm pststrm, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x48,0xa0,0xf8]
+
+prfm #30, [x0, w0, uxtw]
+// CHECK-INST: rprfm #6, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x48,0xa0,0xf8]
+
+prfm #31, [x0, w0, uxtw]
+// CHECK-INST: rprfm #7, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x48,0xa0,0xf8]
+
+prfm #24, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #8, x0, [x0]
+// CHECK-ENCODING: [0x18,0x58,0xa0,0xf8]
+
+prfm #25, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #9, x0, [x0]
+// CHECK-ENCODING: [0x19,0x58,0xa0,0xf8]
+
+prfm #26, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #10, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x58,0xa0,0xf8]
+
+prfm #27, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #11, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x58,0xa0,0xf8]
+
+prfm #28, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #12, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x58,0xa0,0xf8]
+
+prfm #29, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #13, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x58,0xa0,0xf8]
+
+prfm #30, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #14, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x58,0xa0,0xf8]
+
+prfm #31, [x0, w0, uxtw #3]
+// CHECK-INST: rprfm #15, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x58,0xa0,0xf8]
+
+prfm #24, [x0, x0]
+// CHECK-INST: rprfm #16, x0, [x0]
+// CHECK-ENCODING: [0x18,0x68,0xa0,0xf8]
+
+prfm #25, [x0, x0]
+// CHECK-INST: rprfm #17, x0, [x0]
+// CHECK-ENCODING: [0x19,0x68,0xa0,0xf8]
+
+prfm #26, [x0, x0]
+// CHECK-INST: rprfm #18, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x68,0xa0,0xf8]
+
+prfm #27, [x0, x0]
+// CHECK-INST: rprfm #19, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x68,0xa0,0xf8]
+
+prfm #28, [x0, x0]
+// CHECK-INST: rprfm #20, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x68,0xa0,0xf8]
+
+prfm #29, [x0, x0]
+// CHECK-INST: rprfm #21, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x68,0xa0,0xf8]
+
+prfm #30, [x0, x0]
+// CHECK-INST: rprfm #22, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x68,0xa0,0xf8]
+
+prfm #31, [x0, x0]
+// CHECK-INST: rprfm #23, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x68,0xa0,0xf8]
+
+prfm #24, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #24, x0, [x0]
+// CHECK-ENCODING: [0x18,0x78,0xa0,0xf8]
+
+prfm #25, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #25, x0, [x0]
+// CHECK-ENCODING: [0x19,0x78,0xa0,0xf8]
+
+prfm #26, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #26, x0, [x0]
+// CHECK-ENCODING: [0x1a,0x78,0xa0,0xf8]
+
+prfm #27, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #27, x0, [x0]
+// CHECK-ENCODING: [0x1b,0x78,0xa0,0xf8]
+
+prfm #28, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #28, x0, [x0]
+// CHECK-ENCODING: [0x1c,0x78,0xa0,0xf8]
+
+prfm #29, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #29, x0, [x0]
+// CHECK-ENCODING: [0x1d,0x78,0xa0,0xf8]
+
+prfm #30, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #30, x0, [x0]
+// CHECK-ENCODING: [0x1e,0x78,0xa0,0xf8]
+
+prfm #31, [x0, x0, lsl #3]
+// CHECK-INST: rprfm #31, x0, [x0]
+// CHECK-ENCODING: [0x1f,0x78,0xa0,0xf8]
+
+prfm #24, [x0, w0, sxtw]
+// CHECK-INST: rprfm #32, x0, [x0]
+// CHECK-ENCODING: [0x18,0xc8,0xa0,0xf8]
+
+prfm #25, [x0, w0, sxtw]
+// CHECK-INST: rprfm #33, x0, [x0]
+// CHECK-ENCODING: [0x19,0xc8,0xa0,0xf8]
+
+prfm #26, [x0, w0, sxtw]
+// CHECK-INST: rprfm #34, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xc8,0xa0,0xf8]
+
+prfm #27, [x0, w0, sxtw]
+// CHECK-INST: rprfm #35, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xc8,0xa0,0xf8]
+
+prfm #28, [x0, w0, sxtw]
+// CHECK-INST: rprfm #36, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xc8,0xa0,0xf8]
+
+prfm #29, [x0, w0, sxtw]
+// CHECK-INST: rprfm #37, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xc8,0xa0,0xf8]
+
+prfm #30, [x0, w0, sxtw]
+// CHECK-INST: rprfm #38, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xc8,0xa0,0xf8]
+
+prfm #31, [x0, w0, sxtw]
+// CHECK-INST: rprfm #39, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xc8,0xa0,0xf8]
+
+prfm #24, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #40, x0, [x0]
+// CHECK-ENCODING: [0x18,0xd8,0xa0,0xf8]
+
+prfm #25, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #41, x0, [x0]
+// CHECK-ENCODING: [0x19,0xd8,0xa0,0xf8]
+
+prfm #26, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #42, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xd8,0xa0,0xf8]
+
+prfm #27, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #43, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xd8,0xa0,0xf8]
+
+prfm #28, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #44, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xd8,0xa0,0xf8]
+
+prfm #29, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #45, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xd8,0xa0,0xf8]
+
+prfm #30, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #46, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xd8,0xa0,0xf8]
+
+prfm #31, [x0, w0, sxtw #3]
+// CHECK-INST: rprfm #47, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xd8,0xa0,0xf8]
+
+prfm #24, [x0, x0, sxtx]
+// CHECK-INST: rprfm #48, x0, [x0]
+// CHECK-ENCODING: [0x18,0xe8,0xa0,0xf8]
+
+prfm #25, [x0, x0, sxtx]
+// CHECK-INST: rprfm #49, x0, [x0]
+// CHECK-ENCODING: [0x19,0xe8,0xa0,0xf8]
+
+prfm #26, [x0, x0, sxtx]
+// CHECK-INST: rprfm #50, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xe8,0xa0,0xf8]
+
+prfm #27, [x0, x0, sxtx]
+// CHECK-INST: rprfm #51, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xe8,0xa0,0xf8]
+
+prfm #28, [x0, x0, sxtx]
+// CHECK-INST: rprfm #52, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xe8,0xa0,0xf8]
+
+prfm #29, [x0, x0, sxtx]
+// CHECK-INST: rprfm #53, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xe8,0xa0,0xf8]
+
+prfm #30, [x0, x0, sxtx]
+// CHECK-INST: rprfm #54, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xe8,0xa0,0xf8]
+
+prfm #31, [x0, x0, sxtx]
+// CHECK-INST: rprfm #55, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xe8,0xa0,0xf8]
+
+prfm #24, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #56, x0, [x0]
+// CHECK-ENCODING: [0x18,0xf8,0xa0,0xf8]
+
+prfm #25, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #57, x0, [x0]
+// CHECK-ENCODING: [0x19,0xf8,0xa0,0xf8]
+
+prfm #26, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #58, x0, [x0]
+// CHECK-ENCODING: [0x1a,0xf8,0xa0,0xf8]
+
+prfm #27, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #59, x0, [x0]
+// CHECK-ENCODING: [0x1b,0xf8,0xa0,0xf8]
+
+prfm #28, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #60, x0, [x0]
+// CHECK-ENCODING: [0x1c,0xf8,0xa0,0xf8]
+
+prfm #29, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #61, x0, [x0]
+// CHECK-ENCODING: [0x1d,0xf8,0xa0,0xf8]
+
+prfm #30, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #62, x0, [x0]
+// CHECK-ENCODING: [0x1e,0xf8,0xa0,0xf8]
+
+prfm #31, [x0, x0, sxtx #3]
+// CHECK-INST: rprfm #63, x0, [x0]
+// CHECK-ENCODING: [0x1f,0xf8,0xa0,0xf8]
+
Index: llvm/test/MC/AArch64/armv8.9a-cssc.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/armv8.9a-cssc.s
@@ -0,0 +1,98 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-CSSC-ERR %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-CSSC-ERR %s
+
+ abs x0, x1
+// CHECK: abs x0, x1 // encoding: [0x20,0x20,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ abs w0, w1
+// CHECK: abs w0, w1 // encoding: [0x20,0x20,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ cnt x0, x1
+// CHECK: cnt x0, x1 // encoding: [0x20,0x1c,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ cnt w0, w1
+// CHECK: cnt w0, w1 // encoding: [0x20,0x1c,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ ctz x0, x1
+// CHECK: ctz x0, x1 // encoding: [0x20,0x18,0xc0,0xda]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ ctz w0, w1
+// CHECK: ctz w0, w1 // encoding: [0x20,0x18,0xc0,0x5a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+
+ smax x1, x2, x3
+// CHECK: smax x1, x2, x3 // encoding: [0x41,0x60,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smax x1, x2, #3
+// CHECK: smax x1, x2, #3 // encoding: [0x41,0x0c,0xc0,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smax w1, w2, w3
+// CHECK: smax w1, w2, w3 // encoding: [0x41,0x60,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smax w1, w2, #3
+// CHECK: smax w1, w2, #3 // encoding: [0x41,0x0c,0xc0,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin x1, x2, x3
+// CHECK: smin x1, x2, x3 // encoding: [0x41,0x68,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin x1, x2, #3
+// CHECK: smin x1, x2, #3 // encoding: [0x41,0x0c,0xc8,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin w1, w2, w3
+// CHECK: smin w1, w2, w3 // encoding: [0x41,0x68,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin w1, w2, #3
+// CHECK: smin w1, w2, #3 // encoding: [0x41,0x0c,0xc8,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umax x1, x2, x3
+// CHECK: umax x1, x2, x3 // encoding: [0x41,0x64,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umax x1, x2, #3
+// CHECK: umax x1, x2, #3 // encoding: [0x41,0x0c,0xc4,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umax w1, w2, w3
+// CHECK: umax w1, w2, w3 // encoding: [0x41,0x64,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umax w1, w2, #3
+// CHECK: umax w1, w2, #3 // encoding: [0x41,0x0c,0xc4,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin x1, x2, x3
+// CHECK: umin x1, x2, x3 // encoding: [0x41,0x6c,0xc3,0x9a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin x1, x2, #3
+// CHECK: umin x1, x2, #3 // encoding: [0x41,0x0c,0xcc,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin w1, w2, w3
+// CHECK: umin w1, w2, w3 // encoding: [0x41,0x6c,0xc3,0x1a]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin w1, w2, #3
+// CHECK: umin w1, w2, #3 // encoding: [0x41,0x0c,0xcc,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+
+
+ umax wzr, wzr, #255
+// CHECK: umax wzr, wzr, #255 // encoding: [0xff,0xff,0xc7,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umax xzr, xzr, #255
+// CHECK: umax xzr, xzr, #255 // encoding: [0xff,0xff,0xc7,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin xzr, xzr, #255
+// CHECK: umin xzr, xzr, #255 // encoding: [0xff,0xff,0xcf,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ umin wzr, wzr, #255
+// CHECK: umin wzr, wzr, #255 // encoding: [0xff,0xff,0xcf,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smax xzr, xzr, #-1
+// CHECK: smax xzr, xzr, #-1 // encoding: [0xff,0xff,0xc3,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smax wzr, wzr, #-1
+// CHECK: smax wzr, wzr, #-1 // encoding: [0xff,0xff,0xc3,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin xzr, xzr, #-1
+// CHECK: smin xzr, xzr, #-1 // encoding: [0xff,0xff,0xcb,0x91]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
+ smin wzr, wzr, #-1
+// CHECK: smin wzr, wzr, #-1 // encoding: [0xff,0xff,0xcb,0x11]
+// NO-CSSC-ERR: [[@LINE-2]]:13: error: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umin_64_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umin_64_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin x0, x0, x0
+// CHECK-INST: umin x0, x0, x0
+// CHECK-ENCODING: [0x00,0x6c,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin x21, x10, x21
+// CHECK-INST: umin x21, x10, x21
+// CHECK-ENCODING: [0x55,0x6d,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin x23, x13, x8
+// CHECK-INST: umin x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x6d,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin xzr, xzr, xzr
+// CHECK-INST: umin xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x6f,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umin_64_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umin_64_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin x0, x0, #0
+// CHECK-INST: umin x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xcc,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin x21, x10, #85
+// CHECK-INST: umin x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xcd,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin x23, x13, #59
+// CHECK-INST: umin x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xcc,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umin xzr, xzr, #255
+// CHECK-INST: umin xzr, xzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xcf,0x91]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umin_32_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umin_32_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin w0, w0, w0
+// CHECK-INST: umin w0, w0, w0
+// CHECK-ENCODING: [0x00,0x6c,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin w21, w10, w21
+// CHECK-INST: umin w21, w10, w21
+// CHECK-ENCODING: [0x55,0x6d,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin w23, w13, w8
+// CHECK-INST: umin w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x6d,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umin wzr, wzr, wzr
+// CHECK-INST: umin wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x6f,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umin_32_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umin_32_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umin w0, w0, #0
+// CHECK-INST: umin w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xcc,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin w21, w10, #85
+// CHECK-INST: umin w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xcd,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin w23, w13, #59
+// CHECK-INST: umin w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xcc,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umin wzr, wzr, #255
+// CHECK-INST: umin wzr, wzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xcf,0x11]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umax_64_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umax_64_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax x0, x0, x0
+// CHECK-INST: umax x0, x0, x0
+// CHECK-ENCODING: [0x00,0x64,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax x21, x10, x21
+// CHECK-INST: umax x21, x10, x21
+// CHECK-ENCODING: [0x55,0x65,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax x23, x13, x8
+// CHECK-INST: umax x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x65,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax xzr, xzr, xzr
+// CHECK-INST: umax xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x67,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umax_64_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umax_64_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax x0, x0, #0
+// CHECK-INST: umax x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc4,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax x21, x10, #85
+// CHECK-INST: umax x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc5,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax x23, x13, #59
+// CHECK-INST: umax x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc4,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+umax xzr, xzr, #255
+// CHECK-INST: umax xzr, xzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xc7,0x91]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umax_32_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umax_32_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax w0, w0, w0
+// CHECK-INST: umax w0, w0, w0
+// CHECK-ENCODING: [0x00,0x64,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax w21, w10, w21
+// CHECK-INST: umax w21, w10, w21
+// CHECK-ENCODING: [0x55,0x65,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax w23, w13, w8
+// CHECK-INST: umax w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x65,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+umax wzr, wzr, wzr
+// CHECK-INST: umax wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x67,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/umax_32_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/umax_32_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umax w0, w0, #0
+// CHECK-INST: umax w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc4,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax w21, w10, #85
+// CHECK-INST: umax w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc5,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax w23, w13, #59
+// CHECK-INST: umax w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc4,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+umax wzr, wzr, #255
+// CHECK-INST: umax wzr, wzr, #255
+// CHECK-ENCODING: [0xff,0xff,0xc7,0x11]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smin_64_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smin_64_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin x0, x0, x0
+// CHECK-INST: smin x0, x0, x0
+// CHECK-ENCODING: [0x00,0x68,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin x21, x10, x21
+// CHECK-INST: smin x21, x10, x21
+// CHECK-ENCODING: [0x55,0x69,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin x23, x13, x8
+// CHECK-INST: smin x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x69,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin xzr, xzr, xzr
+// CHECK-INST: smin xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x6b,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smin_64_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smin_64_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin x0, x0, #0
+// CHECK-INST: smin x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc8,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin x21, x10, #85
+// CHECK-INST: smin x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc9,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin x23, x13, #59
+// CHECK-INST: smin x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0x91]
+// CHECK-ERROR: instruction requires: cssc
+
+smin xzr, xzr, #-1
+// CHECK-INST: smin xzr, xzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xcb,0x91]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smin_32_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smin_32_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin w0, w0, w0
+// CHECK-INST: smin w0, w0, w0
+// CHECK-ENCODING: [0x00,0x68,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin w21, w10, w21
+// CHECK-INST: smin w21, w10, w21
+// CHECK-ENCODING: [0x55,0x69,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin w23, w13, w8
+// CHECK-INST: smin w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x69,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smin wzr, wzr, wzr
+// CHECK-INST: smin wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x6b,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smin_32_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smin_32_imm.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smin w0, w0, #0
+// CHECK-INST: smin w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc8,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin w21, w10, #85
+// CHECK-INST: smin w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc9,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin w23, w13, #59
+// CHECK-INST: smin w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smin wzr, wzr, #-1
+// CHECK-INST: smin wzr, wzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xcb,0x11]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smax_64_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smax_64_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax x0, x0, x0
+// CHECK-INST: smax x0, x0, x0
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax x21, x10, x21
+// CHECK-INST: smax x21, x10, x21
+// CHECK-ENCODING: [0x55,0x61,0xd5,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax x23, x13, x8
+// CHECK-INST: smax x23, x13, x8
+// CHECK-ENCODING: [0xb7,0x61,0xc8,0x9a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax xzr, xzr, xzr
+// CHECK-INST: smax xzr, xzr, xzr
+// CHECK-ENCODING: [0xff,0x63,0xdf,0x9a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smax_64_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smax_64_imm.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax x0, x0, #0
+// CHECK-INST: smax x0, x0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: 00 00 c0 91 <unknown>
+
+smax x21, x10, #85
+// CHECK-INST: smax x21, x10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc1,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: 55 55 c1 91 <unknown>
+
+smax x23, x13, #59
+// CHECK-INST: smax x23, x13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc0,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: b7 ed c0 91 <unknown>
+
+smax xzr, xzr, #-1
+// CHECK-INST: smax xzr, xzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xc3,0x91]
+// CHECK-ERROR: instruction requires: cssc
+// CHECK-UNKNOWN: ff ff c3 91 <unknown>
+
Index: llvm/test/MC/AArch64/CSSC/smax_32_reg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smax_32_reg.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax w0, w0, w0
+// CHECK-INST: smax w0, w0, w0
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax w21, w10, w21
+// CHECK-INST: smax w21, w10, w21
+// CHECK-ENCODING: [0x55,0x61,0xd5,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax w23, w13, w8
+// CHECK-INST: smax w23, w13, w8
+// CHECK-ENCODING: [0xb7,0x61,0xc8,0x1a]
+// CHECK-ERROR: instruction requires: cssc
+
+smax wzr, wzr, wzr
+// CHECK-INST: smax wzr, wzr, wzr
+// CHECK-ENCODING: [0xff,0x63,0xdf,0x1a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/smax_32_imm.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/smax_32_imm.s
@@ -0,0 +1,34 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding --print-imm-hex=false -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --print-imm-hex=false --mattr=+v9.4a - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: --print-imm-hex=false \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smax w0, w0, #0
+// CHECK-INST: smax w0, w0, #0
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax w21, w10, #85
+// CHECK-INST: smax w21, w10, #85
+// CHECK-ENCODING: [0x55,0x55,0xc1,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax w23, w13, #59
+// CHECK-INST: smax w23, w13, #59
+// CHECK-ENCODING: [0xb7,0xed,0xc0,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
+smax wzr, wzr, #-1
+// CHECK-INST: smax wzr, wzr, #-1
+// CHECK-ENCODING: [0xff,0xff,0xc3,0x11]
+// CHECK-ERROR: instruction requires: cssc
+
Index: llvm/test/MC/AArch64/CSSC/ctz_64.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/ctz_64.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ctz x0, x0
+// CHECK-INST: ctz x0, x0
+// CHECK-ENCODING: [0x00,0x18,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz x21, x10
+// CHECK-INST: ctz x21, x10
+// CHECK-ENCODING: [0x55,0x19,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz x23, x13
+// CHECK-INST: ctz x23, x13
+// CHECK-ENCODING: [0xb7,0x19,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz xzr, xzr
+// CHECK-INST: ctz xzr, xzr
+// CHECK-ENCODING: [0xff,0x1b,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/ctz_32.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/ctz_32.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ctz w0, w0
+// CHECK-INST: ctz w0, w0
+// CHECK-ENCODING: [0x00,0x18,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz w21, w10
+// CHECK-INST: ctz w21, w10
+// CHECK-ENCODING: [0x55,0x19,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz w23, w13
+// CHECK-INST: ctz w23, w13
+// CHECK-ENCODING: [0xb7,0x19,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+ctz wzr, wzr
+// CHECK-INST: ctz wzr, wzr
+// CHECK-ENCODING: [0xff,0x1b,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/cnt_64.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/cnt_64.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+cnt x0, x0
+// CHECK-INST: cnt x0, x0
+// CHECK-ENCODING: [0x00,0x1c,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt x21, x10
+// CHECK-INST: cnt x21, x10
+// CHECK-ENCODING: [0x55,0x1d,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt x23, x13
+// CHECK-INST: cnt x23, x13
+// CHECK-ENCODING: [0xb7,0x1d,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt xzr, xzr
+// CHECK-INST: cnt xzr, xzr
+// CHECK-ENCODING: [0xff,0x1f,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/cnt_32.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/cnt_32.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+cnt w0, w0
+// CHECK-INST: cnt w0, w0
+// CHECK-ENCODING: [0x00,0x1c,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt w21, w10
+// CHECK-INST: cnt w21, w10
+// CHECK-ENCODING: [0x55,0x1d,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt w23, w13
+// CHECK-INST: cnt w23, w13
+// CHECK-ENCODING: [0xb7,0x1d,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+cnt wzr, wzr
+// CHECK-INST: cnt wzr, wzr
+// CHECK-ENCODING: [0xff,0x1f,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/abs_64.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/abs_64.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+abs x0, x0
+// CHECK-INST: abs x0, x0
+// CHECK-ENCODING: [0x00,0x20,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs x21, x10
+// CHECK-INST: abs x21, x10
+// CHECK-ENCODING: [0x55,0x21,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs x23, x13
+// CHECK-INST: abs x23, x13
+// CHECK-ENCODING: [0xb7,0x21,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
+
+abs xzr, xzr
+// CHECK-INST: abs xzr, xzr
+// CHECK-ENCODING: [0xff,0x23,0xc0,0xda]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/test/MC/AArch64/CSSC/abs_32.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/CSSC/abs_32.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
+// RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+abs w0, w0
+// CHECK-INST: abs w0, w0
+// CHECK-ENCODING: [0x00,0x20,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs w21, w10
+// CHECK-INST: abs w21, w10
+// CHECK-ENCODING: [0x55,0x21,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs w23, w13
+// CHECK-INST: abs w23, w13
+// CHECK-ENCODING: [0xb7,0x21,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
+
+abs wzr, wzr
+// CHECK-INST: abs wzr, wzr
+// CHECK-ENCODING: [0xff,0x23,0xc0,0x5a]
+// CHECK-ERROR: instruction requires: cssc
Index: llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
===================================================================
--- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -481,6 +481,14 @@
#include "AArch64GenSystemOperands.inc"
}
+namespace AArch64RPRFM {
+struct RPRFM : SysAlias {
+ using SysAlias::SysAlias;
+};
+#define GET_RPRFM_DECL
+#include "AArch64GenSystemOperands.inc"
+} // namespace AArch64RPRFM
+
namespace AArch64SVEPredPattern {
struct SVEPREDPAT {
const char *Name;
Index: llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -88,6 +88,13 @@
}
}
+namespace llvm {
+ namespace AArch64RPRFM {
+#define GET_RPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+ } // namespace AArch64RPRFM
+} // namespace llvm
+
namespace llvm {
namespace AArch64SVEPredPattern {
#define GET_SVEPREDPAT_IMPL
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -4481,10 +4481,10 @@
}
multiclass sve_int_arith_imm1<bits<2> opc, string asm, SDPatternOperator op> {
- def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8>;
- def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8>;
- def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8>;
- def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8>;
+ def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8_32b>;
+ def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8_32b>;
+ def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8_32b>;
+ def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8_32b>;
def : SVE_1_Op_Imm_Arith_All_Active<nxv16i8, nxv16i1, op, ZPR8, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _B)>;
def : SVE_1_Op_Imm_Arith_All_Active<nxv8i16, nxv8i1, op, ZPR16, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _H)>;
@@ -4505,10 +4505,10 @@
}
multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> {
- def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>;
- def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
- def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
- def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
+ def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8_32b>;
+ def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8_32b>;
+ def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8_32b>;
+ def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8_32b>;
def : SVE_1_Op_Imm_Arith_All_Active<nxv16i8, nxv16i1, op, ZPR8, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _B)>;
def : SVE_1_Op_Imm_Arith_All_Active<nxv8i16, nxv8i1, op, ZPR16, i32, SVEArithSImmPat32, !cast<Instruction>(NAME # _H)>;
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -53,6 +53,8 @@
protected:
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
+ bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
+ raw_ostream &O, StringRef Annot);
// Operand printers
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
@@ -138,6 +140,9 @@
void printPrefetchOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printRPRFMOperand(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+
void printPSBHintOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -81,6 +81,12 @@
return;
}
+ // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
+ if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
+ if (printRangePrefetchAlias(MI, STI, O, Annot))
+ return;
+ }
+
// SBFM/UBFM should print to a nicer aliased form if possible.
if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
@@ -808,6 +814,56 @@
AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
}
+bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O,
+ StringRef Annot) {
+ unsigned Opcode = MI->getOpcode();
+
+#ifndef NDEBUG
+ assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
+ "Invalid opcode for RPRFM alias!");
+#endif
+
+ unsigned PRFOp = MI->getOperand(0).getImm();
+ unsigned Mask = 0x18; // 0b11000
+ if ((PRFOp & Mask) != Mask)
+ return false; // Rt != '11xxx', it's a PRFM instruction.
+
+ unsigned Rm = MI->getOperand(2).getReg();
+
+ // "Rm" must be a 64-bit GPR for RPRFM.
+ if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
+ Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
+ &MRI.getRegClass(AArch64::GPR64RegClassID));
+
+ unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
+ unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
+
+ assert((SignExtend <= 1) && "sign extend should be a single bit!");
+ assert((Shift <= 1) && "Shift should be a single bit!");
+
+ unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
+
+ // encoded in "option<2>:option<0>:S:Rt<2:0>".
+ unsigned RPRFOp =
+ (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
+
+ O << "\trprfm ";
+ if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
+ O << RPRFM->Name << ", ";
+ else
+ O << "#" << formatImm(RPRFOp) << ", ";
+ O << getRegisterName(Rm);
+ O << ", [";
+ printOperand(MI, 1, STI, O); // "Rn".
+ O << "]";
+
+ printAnnotation(O, Annot);
+
+ return true;
+}
+
bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -1289,6 +1345,18 @@
O << ']';
}
+void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned prfop = MI->getOperand(OpNum).getImm();
+ if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
+ O << PRFM->Name;
+ return;
+ }
+
+ O << '#' << formatImm(prfop);
+}
+
template <bool IsSVEPrefetch>
void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
Index: llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -282,6 +282,9 @@
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr,
const MCDisassembler *Decoder);
+static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
#include "AArch64GenDisassemblerTables.inc"
#include "AArch64GenInstrInfo.inc"
@@ -1997,3 +2000,37 @@
return MCDisassembler::Success;
}
+
+static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
+ uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ // PRFM with Rt = '11xxx' should be decoded as RPRFM.
+ // Fail to decode and defer to fallback decoder table to decode RPRFM.
+ unsigned Mask = 0x18;
+ uint64_t Rt = fieldFromInstruction(insn, 0, 5);
+ if ((Rt & Mask) == Mask)
+ return Fail;
+
+ uint64_t Rn = fieldFromInstruction(insn, 5, 5);
+ uint64_t Shift = fieldFromInstruction(insn, 12, 1);
+ uint64_t Extend = fieldFromInstruction(insn, 15, 1);
+ uint64_t Rm = fieldFromInstruction(insn, 16, 5);
+
+ Inst.addOperand(MCOperand::createImm(Rt));
+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+
+ switch (Inst.getOpcode()) {
+ default:
+ return Fail;
+ case AArch64::PRFMroW:
+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+ break;
+ case AArch64::PRFMroX:
+ DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+ break;
+ }
+
+ DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
+
+ return Success;
+}
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -252,6 +252,7 @@
OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
template <bool IsSVEPrefetch = false>
OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
+ OperandMatchResultTy tryParseRPRFMOperand(OperandVector &Operands);
OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
OperandMatchResultTy tryParseBTIHint(OperandVector &Operands);
OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
@@ -2943,6 +2944,56 @@
return MatchOperand_Success;
}
+// Either an identifier for named values or a 6-bit immediate.
+OperandMatchResultTy
+AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ const AsmToken &Tok = getTok();
+
+ unsigned MaxVal = 63;
+
+ // Immediate case, with optional leading hash:
+ if (parseOptionalToken(AsmToken::Hash) ||
+ Tok.is(AsmToken::Integer)) {
+ const MCExpr *ImmVal;
+ if (getParser().parseExpression(ImmVal))
+ return MatchOperand_ParseFail;
+
+ const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
+ if (!MCE) {
+ TokError("immediate value expected for prefetch operand");
+ return MatchOperand_ParseFail;
+ }
+ unsigned prfop = MCE->getValue();
+ if (prfop > MaxVal) {
+ TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
+ "] expected");
+ return MatchOperand_ParseFail;
+ }
+
+ auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(MCE->getValue());
+ Operands.push_back(AArch64Operand::CreatePrefetch(
+ prfop, RPRFM ? RPRFM->Name : "", S, getContext()));
+ return MatchOperand_Success;
+ }
+
+ if (Tok.isNot(AsmToken::Identifier)) {
+ TokError("prefetch hint expected");
+ return MatchOperand_ParseFail;
+ }
+
+ auto RPRFM = AArch64RPRFM::lookupRPRFMByName(Tok.getString());
+ if (!RPRFM) {
+ TokError("prefetch hint expected");
+ return MatchOperand_ParseFail;
+ }
+
+ Operands.push_back(AArch64Operand::CreatePrefetch(
+ RPRFM->Encoding, Tok.getString(), S, getContext()));
+ Lex(); // Eat identifier token.
+ return MatchOperand_Success;
+}
+
/// tryParsePrefetch - Try to parse a prefetch operand.
template <bool IsSVEPrefetch>
OperandMatchResultTy
Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -287,6 +287,26 @@
def : SVEPRFM<"pstl3strm", 0x0d>;
}
+//===----------------------------------------------------------------------===//
+// RPRFM (prefetch) instruction options.
+//===----------------------------------------------------------------------===//
+
+class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> : SearchableTable {
+ let SearchableFields = ["Name", "Encoding"];
+ let EnumValueField = "Encoding";
+
+ string Name = name;
+ bits<6> Encoding;
+ let Encoding{0} = type_encoding;
+ let Encoding{5-1} = policy_encoding;
+ code Requires = [{ {} }];
+}
+
+def : RPRFM<"pldkeep", 0b0, 0b00000>;
+def : RPRFM<"pstkeep", 0b1, 0b00000>;
+def : RPRFM<"pldstrm", 0b0, 0b00010>;
+def : RPRFM<"pststrm", 0b1, 0b00010>;
+
//===----------------------------------------------------------------------===//
// SVE Predicate patterns
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -13,6 +13,8 @@
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
//
+def HasV8_0a : Predicate<"Subtarget->hasV8_0aOps()">,
+ AssemblerPredicate<(all_of HasV8_0aOps), "armv8.0a">;
def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
AssemblerPredicateWithAll<(all_of HasV8_1aOps), "armv8.1a">;
def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
@@ -113,6 +115,8 @@
AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;
def HasCRC : Predicate<"Subtarget->hasCRC()">,
AssemblerPredicateWithAll<(all_of FeatureCRC), "crc">;
+def HasCSSC : Predicate<"Subtarget->hasCSSC()">,
+ AssemblerPredicateWithAll<(all_of FeatureCSSC), "cssc">;
def HasLSE : Predicate<"Subtarget->hasLSE()">,
AssemblerPredicateWithAll<(all_of FeatureLSE), "lse">;
def HasNoLSE : Predicate<"!Subtarget->hasLSE()">;
@@ -2009,12 +2013,11 @@
// v8.5 Memory Tagging Extension
let Predicates = [HasMTE] in {
-def IRG : BaseTwoOperand<0b0100, GPR64sp, "irg", int_aarch64_irg, GPR64sp, GPR64>,
- Sched<[]>{
- let Inst{31} = 1;
-}
-def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", int_aarch64_gmi, GPR64sp>, Sched<[]>{
- let Inst{31} = 1;
+def IRG : BaseTwoOperandRegReg<0b1, 0b0, 0b000100, GPR64sp, "irg",
+ int_aarch64_irg, GPR64sp, GPR64>, Sched<[]>;
+
+def GMI : BaseTwoOperandRegReg<0b1, 0b0, 0b000101, GPR64, "gmi",
+ int_aarch64_gmi, GPR64sp>, Sched<[]> {
let isNotDuplicable = 1;
}
def ADDG : AddSubG<0, "addg", null_frag>;
@@ -2180,13 +2183,13 @@
// One operand data processing instructions.
//===----------------------------------------------------------------------===//
-defm CLS : OneOperandData<0b101, "cls">;
-defm CLZ : OneOperandData<0b100, "clz", ctlz>;
-defm RBIT : OneOperandData<0b000, "rbit", bitreverse>;
+defm CLS : OneOperandData<0b000101, "cls">;
+defm CLZ : OneOperandData<0b000100, "clz", ctlz>;
+defm RBIT : OneOperandData<0b000000, "rbit", bitreverse>;
-def REV16Wr : OneWRegData<0b001, "rev16",
- UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
-def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
+def REV16Wr : OneWRegData<0b000001, "rev16",
+ UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
+def REV16Xr : OneXRegData<0b000001, "rev16", null_frag>;
def : Pat<(cttz GPR32:$Rn),
(CLZWr (RBITWr GPR32:$Rn))>;
@@ -2204,10 +2207,10 @@
// Unlike the other one operand instructions, the instructions with the "rev"
// mnemonic do *not* just different in the size bit, but actually use different
// opcode bits for the different sizes.
-def REVWr : OneWRegData<0b010, "rev", bswap>;
-def REVXr : OneXRegData<0b011, "rev", bswap>;
-def REV32Xr : OneXRegData<0b010, "rev32",
- UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
+def REVWr : OneWRegData<0b000010, "rev", bswap>;
+def REVXr : OneXRegData<0b000011, "rev", bswap>;
+def REV32Xr : OneXRegData<0b000010, "rev32",
+ UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
@@ -8482,6 +8485,47 @@
def : Pat<(AArch64AssertZExtBool GPR32:$op),
(i32 GPR32:$op)>;
+//===----------------------------===//
+// 2022 Architecture Extensions:
+//===----------------------------===//
+
+//===----------------------------------------------------------------------===//
+// General Data-Processing Instructions (FEAT_V94_DP)
+//===----------------------------------------------------------------------===//
+defm ABS : OneOperandData<0b001000, "abs">, Requires<[HasCSSC]>;
+defm CNT : OneOperandData<0b000111, "cnt">, Requires<[HasCSSC]>;
+defm CTZ : OneOperandData<0b000110, "ctz">, Requires<[HasCSSC]>;
+
+defm SMAX : ComparisonOp<0, 0, "smax">, Requires<[HasCSSC]>;
+defm SMIN : ComparisonOp<0, 1, "smin">, Requires<[HasCSSC]>;
+defm UMAX : ComparisonOp<1, 0, "umax">, Requires<[HasCSSC]>;
+defm UMIN : ComparisonOp<1, 1, "umin">, Requires<[HasCSSC]>;
+
+def RPRFM:
+ I<(outs), (ins rprfop:$Rt, GPR64:$Rm, GPR64sp:$Rn),
+ "rprfm", "\t$Rt, $Rm, [$Rn]", "", []>,
+ Sched<[]> {
+ bits<6> Rt;
+ bits<5> Rn;
+ bits<5> Rm;
+ let Inst{2-0} = Rt{2-0};
+ let Inst{4-3} = 0b11;
+ let Inst{9-5} = Rn;
+ let Inst{11-10} = 0b10;
+ let Inst{13-12} = Rt{4-3};
+ let Inst{14} = 0b1;
+ let Inst{15} = Rt{5};
+ let Inst{20-16} = Rm;
+ let Inst{31-21} = 0b11111000101;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 1;
+ // RPRFM overlaps with PRFM (reg), when the decoder method of PRFM returns
+ // Fail, the decoder should attempt to decode RPRFM. This requires setting
+ // the decoder namespace to "Fallback".
+ let DecoderNamespace = "Fallback";
+}
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -294,7 +294,6 @@
let PredicateMethod = "isSImm<" # width # ">";
}
-
class AsmImmRange<int Low, int High> : AsmOperandClass {
let Name = "Imm" # Low # "_" # High;
let DiagnosticType = "InvalidImm" # Low # "_" # High;
@@ -336,8 +335,22 @@
let DecoderMethod = "DecodeSImm<9>";
}
+// imm0_255 predicate - True if the immediate is in the range [0,255].
+def Imm0_255Operand : AsmImmRange<0,255>;
+
+def uimm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
+ let ParserMatchClass = Imm0_255Operand;
+}
+def uimm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 256; }]> {
+ let ParserMatchClass = Imm0_255Operand;
+}
+
def SImm8Operand : SImmOperand<8>;
-def simm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
+def simm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
+ let ParserMatchClass = SImm8Operand;
+ let DecoderMethod = "DecodeSImm<8>";
+}
+def simm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 128; }]> {
let ParserMatchClass = SImm8Operand;
let DecoderMethod = "DecodeSImm<8>";
}
@@ -863,9 +876,6 @@
}]>;
}
-// imm0_255 predicate - True if the immediate is in the range [0,255].
-def Imm0_255Operand : AsmImmRange<0,255>;
-
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 256;
}]> {
@@ -1816,6 +1826,19 @@
let Inst{7-5} = op2;
}
+def RangePrefetchOperand : AsmOperandClass {
+ let Name = "RangePrefetch";
+ let ParserMethod = "tryParseRPRFMOperand";
+ let PredicateMethod = "isPrefetch";
+ let RenderMethod = "addPrefetchOperands";
+}
+
+def rprfop : Operand<i32>, TImmLeaf<i32, [{
+ return (((uint32_t)Imm) <= 63);
+ }]> {
+ let PrintMethod = "printRPRFMOperand";
+ let ParserMatchClass = RangePrefetchOperand;
+}
// Branch (register) instructions:
//
@@ -2124,7 +2147,8 @@
//---
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
-class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
+class BaseOneOperandData<bit sf, bit S, bits<5> opc2, bits<6> opc,
+ RegisterClass regtype, string asm,
SDPatternOperator node>
: I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
[(set regtype:$Rd, (node regtype:$Rn))]>,
@@ -2132,33 +2156,29 @@
bits<5> Rd;
bits<5> Rn;
- let Inst{30-13} = 0b101101011000000000;
- let Inst{12-10} = opc;
+ let Inst{31} = sf;
+ let Inst{30} = 0b1;
+ let Inst{29} = S;
+ let Inst{28-21} = 0b11010110;
+ let Inst{20-16} = opc2;
+ let Inst{15-10} = opc;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
-multiclass OneOperandData<bits<3> opc, string asm,
+multiclass OneOperandData<bits<6> opc, string asm,
SDPatternOperator node = null_frag> {
- def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
- let Inst{31} = 0;
- }
+ def Wr : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
- def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
- let Inst{31} = 1;
- }
+ def Xr : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
}
-class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
- : BaseOneOperandData<opc, GPR32, asm, node> {
- let Inst{31} = 0;
-}
+class OneWRegData<bits<6> opc, string asm, SDPatternOperator node>
+ : BaseOneOperandData<0b0, 0b0, 0b00000, opc, GPR32, asm, node>;
-class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
- : BaseOneOperandData<opc, GPR64, asm, node> {
- let Inst{31} = 1;
-}
+class OneXRegData<bits<6> opc, string asm, SDPatternOperator node>
+ : BaseOneOperandData<0b1, 0b0, 0b00000, opc, GPR64, asm, node>;
class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm,
SDPatternOperator op>
@@ -2295,56 +2315,51 @@
}
}
-class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
- SDPatternOperator OpNode,
- RegisterClass in1regtype = regtype,
- RegisterClass in2regtype = regtype>
+class BaseTwoOperandRegReg<bit sf, bit S, bits<6> opc, RegisterClass regtype,
+ string asm, SDPatternOperator OpNode,
+ RegisterClass in1regtype = regtype,
+ RegisterClass in2regtype = regtype>
: I<(outs regtype:$Rd), (ins in1regtype:$Rn, in2regtype:$Rm),
asm, "\t$Rd, $Rn, $Rm", "",
[(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
bits<5> Rd;
bits<5> Rn;
bits<5> Rm;
- let Inst{30-21} = 0b0011010110;
+ let Inst{31} = sf;
+ let Inst{30} = 0b0;
+ let Inst{29} = S;
+ let Inst{28-21} = 0b11010110;
let Inst{20-16} = Rm;
- let Inst{15-14} = 0b00;
- let Inst{13-10} = opc;
+ let Inst{15-10} = opc;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
-class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
+class BaseDiv<bit size, bit isSigned, RegisterClass regtype, string asm,
SDPatternOperator OpNode>
- : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
+ : BaseTwoOperandRegReg<size, 0b0, {0,0,0,0,1,?}, regtype, asm, OpNode> {
let Inst{10} = isSigned;
}
multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
- def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
- Sched<[WriteID32, ReadID, ReadID]> {
- let Inst{31} = 0;
- }
- def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
- Sched<[WriteID64, ReadID, ReadID]> {
- let Inst{31} = 1;
- }
+ def Wr : BaseDiv<0b0, isSigned, GPR32, asm, OpNode>,
+ Sched<[WriteID32, ReadID, ReadID]>;
+
+ def Xr : BaseDiv<0b1, isSigned, GPR64, asm, OpNode>,
+ Sched<[WriteID64, ReadID, ReadID]>;
}
-class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
+class BaseShift<bit size, bits<2> shift_type, RegisterClass regtype, string asm,
SDPatternOperator OpNode = null_frag>
- : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
+ : BaseTwoOperandRegReg<size, 0b0, {0,0,1,0,?,?}, regtype, asm, OpNode>,
Sched<[WriteIS, ReadI]> {
let Inst{11-10} = shift_type;
}
multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
- def Wr : BaseShift<shift_type, GPR32, asm> {
- let Inst{31} = 0;
- }
+ def Wr : BaseShift<0b0, shift_type, GPR32, asm>;
- def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
- let Inst{31} = 1;
- }
+ def Xr : BaseShift<0b1, shift_type, GPR64, asm, OpNode>;
def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
(!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
@@ -2874,10 +2889,8 @@
}
class SUBP<bit setsFlags, string asm_instr, SDPatternOperator OpNode>
- : BaseTwoOperand<0b0000, GPR64, asm_instr, OpNode, GPR64sp, GPR64sp> {
- let Inst{31} = 1;
- let Inst{29} = setsFlags;
-}
+ : BaseTwoOperandRegReg<0b1, setsFlags, 0b000000, GPR64, asm_instr, OpNode,
+ GPR64sp, GPR64sp>;
//---
// Extract
@@ -3992,6 +4005,11 @@
let Inst{11-10} = 0b10;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
+ let DecoderMethod = "DecodePRFMRegInstruction";
+ // PRFM (reg) aliases with RPRFM added to the base A64 instruction set. When
+ // the decoder method returns Fail, the decoder should attempt to decode the
+ // instruction as RPRFM.
+ let hasCompleteDecoder = 0;
}
multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
@@ -11676,6 +11694,70 @@
def TN : MOPSMemorySetTagging<opcode, 1, 1, asm # "tn">;
}
+//---
+// 2022 Architecture Extensions: General Data Processing (FEAT_CSSC)
+//---
+
+class BaseTwoOperandRegImm<bit sf, bit Op, bit S, bits<4> opc,
+ RegisterClass regtype, ImmLeaf immtype, string asm,
+ SDPatternOperator OpNode>
+ : I<(outs regtype:$Rd), (ins regtype:$Rn, immtype:$imm),
+ asm, "\t$Rd, $Rn, $imm", "",
+ [(set regtype:$Rd, (OpNode regtype:$Rn, immtype:$imm))]> {
+ bits<5> Rd;
+ bits<5> Rn;
+ bits<8> imm;
+
+ let Inst{31} = sf;
+ let Inst{30} = Op;
+ let Inst{29} = S;
+ let Inst{28-22} = 0b1000111;
+ let Inst{21-18} = opc;
+ let Inst{17-10} = imm;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rd;
+}
+
+class BaseComparisonOpReg<bit size, bit isUnsigned, bit isMin,
+ RegisterClass regtype, string asm,
+ SDPatternOperator OpNode>
+ : BaseTwoOperandRegReg<size, 0b0, {0,1,1,0,?,?}, regtype, asm, OpNode>,
+ Sched<[WriteI]> {
+ let Inst{11} = isMin;
+ let Inst{10} = isUnsigned;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+}
+
+class BaseComparisonOpImm<bit size, bit isUnsigned, bit isMin,
+ RegisterClass regtype, ImmLeaf immtype, string asm,
+ SDPatternOperator OpNode>
+ : BaseTwoOperandRegImm<size, 0b0, 0b0, {0,0,?,?}, regtype, immtype, asm,
+ OpNode>,
+ Sched<[]> {
+ let Inst{19} = isMin;
+ let Inst{18} = isUnsigned;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+}
+
+multiclass ComparisonOp<bit isUnsigned, bit isMin, string asm,
+ SDPatternOperator OpNode = null_frag> {
+ def Wrr : BaseComparisonOpReg<0b0, isUnsigned, isMin, GPR32, asm, OpNode>;
+
+ def Wri : BaseComparisonOpImm<0b0, isUnsigned, isMin, GPR32,
+ !cond(isUnsigned : uimm8_32b,
+ !not(isUnsigned) : simm8_32b), asm, OpNode>;
+
+ def Xrr : BaseComparisonOpReg<0b1, isUnsigned, isMin, GPR64, asm, OpNode>;
+
+ def Xri : BaseComparisonOpImm<0b1, isUnsigned, isMin, GPR64,
+ !cond(isUnsigned : uimm8_64b,
+ !not(isUnsigned) : simm8_64b), asm, OpNode>;
+}
+
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -493,6 +493,9 @@
def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
"Enable Exception Level 3">;
+def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true",
+ "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
+
def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
"FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
@@ -549,7 +552,7 @@
def HasV8_9aOps : SubtargetFeature<
"v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
- [HasV8_8aOps]>;
+ [HasV8_8aOps, FeatureCSSC]>;
def HasV9_0aOps : SubtargetFeature<
"v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===================================================================
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -75,7 +75,8 @@
AEK_SVE2p1 = 1ULL << 44, // FEAT_SVE2p1
AEK_SME2p1 = 1ULL << 45, // FEAT_SME2p1
AEK_B16B16 = 1ULL << 46, // FEAT_B16B16
- AEK_SMEF16F16 = 1ULL << 47 // FEAT_SMEF16F16
+ AEK_SMEF16F16 = 1ULL << 47, // FEAT_SMEF16F16
+ AEK_CSSC = 1ULL << 48, // FEAT_CSSC
};
enum class ArchKind {
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===================================================================
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -151,6 +151,7 @@
AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC, "+hbc", "-hbc")
AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops")
AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon")
+AARCH64_ARCH_EXT_NAME("cssc", AArch64::AEK_CSSC, "+cssc", "-cssc")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
Index: clang/test/Driver/aarch64-cssc.c
===================================================================
--- /dev/null
+++ clang/test/Driver/aarch64-cssc.c
@@ -0,0 +1,15 @@
+// Test that target feature cssc is implemented and available correctly
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+
+// CHECK: "-target-feature" "+cssc"
+// NO_CSSC: "-target-feature" "-cssc"
+// ABSENT_CSSC-NOT: "-target-feature" "+cssc"
+// ABSENT_CSSC-NOT: "-target-feature" "-cssc"
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
