4vtomat updated this revision to Diff 486169.
4vtomat added a comment.
Address Eric's comments!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138807/new/
https://reviews.llvm.org/D138807
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rvv/zvkb.s
llvm/test/MC/RISCV/rvv/zvkg.s
llvm/test/MC/RISCV/rvv/zvknh.s
llvm/test/MC/RISCV/rvv/zvkns-invalid.s
llvm/test/MC/RISCV/rvv/zvkns.s
llvm/test/MC/RISCV/rvv/zvksed-invalid.s
llvm/test/MC/RISCV/rvv/zvksed.s
llvm/test/MC/RISCV/rvv/zvksh.s
Index: llvm/test/MC/RISCV/rvv/zvksh.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae <unknown>
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82 <unknown>
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86 <unknown>
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2 <unknown>
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6 <unknown>
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaesdf.vv v10, v9
+# CHECK-INST: vaesdf.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 90 a2 <unknown>
+
+vaesdf.vs v10, v9
+# CHECK-INST: vaesdf.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 90 a6 <unknown>
+
+vaesef.vv v10, v9
+# CHECK-INST: vaesef.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 91 a2 <unknown>
+
+vaesef.vs v10, v9
+# CHECK-INST: vaesef.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 91 a6 <unknown>
+
+vaesdm.vv v10, v9
+# CHECK-INST: vaesdm.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x90,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 25 90 a2 <unknown>
+
+vaesdm.vs v10, v9
+# CHECK-INST: vaesdm.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x90,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 25 90 a6 <unknown>
+
+vaesem.vv v10, v9
+# CHECK-INST: vaesem.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x91,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 25 91 a2 <unknown>
+
+vaesem.vs v10, v9
+# CHECK-INST: vaesem.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x91,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 25 91 a6 <unknown>
+
+vaeskf1.vi v10, v9, 1
+# CHECK-INST: vaeskf1.vi v10, v9, 1
+# CHECK-ENCODING: [0x77,0xa5,0x90,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 90 8a <unknown>
+
+vaeskf2.vi v10, v9, 2
+# CHECK-INST: vaeskf2.vi v10, v9, 2
+# CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 25 91 aa <unknown>
+
+vaesz.vs v10, v9
+# CHECK-INST: vaesz.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 93 a6 <unknown>
Index: llvm/test/MC/RISCV/rvv/zvkns-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/zvknh.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvknh.s
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvknha - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvknhb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsha2ms.vv v10, v9, v8
+# CHECK-INST: vsha2ms.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xb6]
+# CHECK-UNKNOWN: 77 25 94 b6 <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) or 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+
+vsha2ch.vv v10, v9, v8
+# CHECK-INST: vsha2ch.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xba]
+# CHECK-UNKNOWN: 77 25 94 ba <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) or 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+
+vsha2cl.vv v10, v9, v8
+# CHECK-INST: vsha2cl.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xbe]
+# CHECK-UNKNOWN: 77 25 94 be <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) or 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
Index: llvm/test/MC/RISCV/rvv/zvkg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkg.s
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkg - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vghmac.vv v10, v9, v8
+# CHECK-INST: vghmac.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvkg'
+# CHECK-UNKNOWN: 77 25 94 b2 <unknown>
Index: llvm/test/MC/RISCV/rvv/zvkb.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkb.s
@@ -0,0 +1,93 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 04 <unknown>
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 04 <unknown>
+
+vandn.vi v10, v9, 7, v0.t
+# CHECK-INST: vandn.vi v10, v9, 7, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x93,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 b5 93 04 <unknown>
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 25 94 48 <unknown>
+
+vclmul.vv v10, v9, v8
+# CHECK-INST: vclmul.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 25 94 32 <unknown>
+
+vclmul.vx v10, v9, a0
+# CHECK-INST: vclmul.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 65 95 32 <unknown>
+
+vclmulh.vv v10, v9, v8
+# CHECK-INST: vclmulh.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 25 94 36 <unknown>
+
+vclmulh.vx v10, v9, a0
+# CHECK-INST: vclmulh.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 65 95 36 <unknown>
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 a5 94 48 <unknown>
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 54 <unknown>
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 54 <unknown>
+
+vror.vv v10, v9, v8, v0.t
+# CHECK-INST: vror.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 50 <unknown>
+
+vror.vx v10, v9, a0, v0.t
+# CHECK-INST: vror.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 50 <unknown>
+
+vror.vi v10, v9, 33, v0.t
+# CHECK-INST: vror.vi v10, v9, 33, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 b5 90 54 <unknown>
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -107,6 +107,27 @@
.attribute arch, "rv32izbc1p0"
# CHECK: attribute 5, "rv32i2p0_zbc1p0"
+.attribute arch, "rv32i_zve64x_zvkb0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p1_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvkg0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkg0p1_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvknha0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvknha0p1_zvl32b1p0"
+
+.attribute arch, "rv32i_zve64x_zvknhb0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknhb0p1_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvkns0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkns0p1_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksed0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksed0p1_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksh0p1"
+# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksh0p1_zvl32b1p0"
+
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p0_zbs1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -41,6 +41,13 @@
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkns %s -o - | FileCheck --check-prefix=RV32ZVKNS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -85,6 +92,13 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkns %s -o - | FileCheck --check-prefix=RV64ZVKNS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -126,6 +140,13 @@
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
+; RV32ZVKB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p1_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p1_zvl32b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p1_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p1_zvknhb0p1_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNS: .attribute 5, "rv32i2p0_zve32x1p0_zvkns0p1_zvl32b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p1_zvl32b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p1_zvl32b1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -171,6 +192,13 @@
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
+; RV64ZVKB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p1_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p1_zvl32b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p1_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p1_zvknhb0p1_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNS: .attribute 5, "rv64i2p0_zve32x1p0_zvkns0p1_zvl32b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p1_zvl32b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p1_zvl32b1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -0,0 +1,175 @@
+//===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zvk',
+// Vector Cryptography Instructions extension, version 0.1.
+//
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+multiclass VALU_IV_V_X_VCLMUL<string opcodestr, bits<6> funct6> {
+ def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
+ Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUV_UpperBound, ReadVMask]>;
+ def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
+ Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUX_UpperBound, ReadVMask]>;
+}
+
+class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<6> imm;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-27} = funct6{5-1};
+ let Inst{26} = imm{5};
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = imm{4-0};
+ let Inst{14-12} = OPIVI.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
+}
+
+multiclass VALU_IV_V_X_I_VROR<string opcodestr, bits<6> funct6,
+ Operand optype = uimm6, string vw = "v">
+ : VALU_IV_V_X<opcodestr, funct6> {
+ def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
+ (ins VR:$vs2, optype:$imm, VMaskOp:$vm),
+ opcodestr # "." # vw # "i", "$vd, $vs2, $imm$vm">,
+ Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
+ ReadVMask]>;
+}
+
+// op vd, vs2, vs1
+class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : VALUVVNoVm<funct6, opv, opcodestr> {
+ let Opcode = OPC_OP_P.Value;
+}
+
+// op vd, vs2, imm, vm
+class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : VALUVINoVm<funct6, opcodestr, optype> {
+ let Opcode = OPC_OP_P.Value;
+ let Inst{14-12} = OPMVV.Value;
+}
+
+// op vd, vs2 (use vs1 as instruction encoding)
+class PALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+ : VALUVs2NoVm<funct6, vs1, opv, opcodestr> {
+ let Opcode = OPC_OP_P.Value;
+}
+
+multiclass PALUVvVs2NoVm<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
+ RISCVVFormat opv, string opcodestr> {
+ let Opcode = OPC_OP_P.Value in {
+ def NAME # _VV : VALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
+ def NAME # _VS : VALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
+ }
+}
+
+// vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need
+// to customize one for them.
+class PALUVI_CUSTOM<bits<6> funct6, string opcodestr, Operand optype>
+ : VALUVINoVm<funct6, opcodestr, optype> {
+ let Opcode = OPC_OP_P.Value;
+ let Inst{14-12} = OPMVV.Value;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+def RnumArg_0_7 : AsmOperandClass {
+ let Name = "RnumArg_0_7";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidRnumArg_0_7";
+}
+
+def RnumArg_1_10 : AsmOperandClass {
+ let Name = "RnumArg_1_10";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidRnumArg_1_10";
+}
+
+def RnumArg_2_14 : AsmOperandClass {
+ let Name = "RnumArg_2_14";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidRnumArg_2_14";
+}
+
+def rnum_0_7 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (0 <= Imm && Imm <= 7);}]> {
+ let ParserMatchClass = RnumArg_0_7;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM_0_7";
+ let OperandNamespace = "RISCVOp";
+}
+
+def rnum_1_10 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (1 <= Imm && Imm <= 10);}]> {
+ let ParserMatchClass = RnumArg_1_10;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM_1_10";
+ let OperandNamespace = "RISCVOp";
+}
+
+def rnum_2_14 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (2 <= Imm && Imm <= 14);}]> {
+ let ParserMatchClass = RnumArg_2_14;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM_2_14";
+ let OperandNamespace = "RISCVOp";
+}
+
+let Predicates = [HasStdExtZvkb] in {
+ defm VANDN_V : VALU_IV_V_X_I<"vandn", 0b000001>;
+ def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
+ defm VCLMUL_V : VALU_IV_V_X_VCLMUL<"vclmul", 0b001100>;
+ defm VCLMULH_V : VALU_IV_V_X_VCLMUL<"vclmulh", 0b001101>;
+ def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
+ defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
+ defm VROR_V : VALU_IV_V_X_I_VROR<"vror", 0b010100>;
+} // Predicates = [HasStdExtZvkb]
+
+let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
+ def VGHMAC_VV : PALUVVNoVm<0b101100, OPMVV, "vghmac.vv">;
+} // Predicates = [HasStdExtZvkg]
+
+let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = NoConstraint in {
+ def VSHA2CH_VV : PALUVVNoVm<0b101110, OPMVV, "vsha2ch.vv">;
+ def VSHA2CL_VV : PALUVVNoVm<0b101111, OPMVV, "vsha2cl.vv">;
+ def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">;
+} // Predicates = [HasStdExtZvknhaOrZvknhb]
+
+let Predicates = [HasStdExtZvkns], RVVConstraint = NoConstraint in {
+ def VAESDF_VV : PALUVs2NoVm<0b101000, 0b00001, OPMVV, "vaesdf.vv">;
+ def VAESDF_VS : PALUVs2NoVm<0b101001, 0b00001, OPMVV, "vaesdf.vs">;
+ def VAESDM_VV : PALUVs2NoVm<0b101000, 0b00000, OPMVV, "vaesdm.vv">;
+ def VAESDM_VS : PALUVs2NoVm<0b101001, 0b00000, OPMVV, "vaesdm.vs">;
+ def VAESEF_VV : PALUVs2NoVm<0b101000, 0b00011, OPMVV, "vaesef.vv">;
+ def VAESEF_VS : PALUVs2NoVm<0b101001, 0b00011, OPMVV, "vaesef.vs">;
+ def VAESEM_VV : PALUVs2NoVm<0b101000, 0b00010, OPMVV, "vaesem.vv">;
+ def VAESEM_VS : PALUVs2NoVm<0b101001, 0b00010, OPMVV, "vaesem.vs">;
+ def VAESKF1_VI : PALUVI_CUSTOM<0b100010, "vaeskf1.vi", rnum_1_10>;
+ def VAESKF2_VI : PALUVI_CUSTOM<0b101010, "vaeskf2.vi", rnum_2_14>;
+ def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
+} // Predicates = [HasStdExtZvkns]
+
+let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
+ def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
+ defm VSM4R : PALUVvVs2NoVm<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
+} // Predicates = [HasStdExtZvksed]
+
+let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in {
+ def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
+ def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
+} // Predicates = [HasStdExtZvksh]
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -410,6 +410,14 @@
: RVInstV<funct6, vs1, opv, (outs VR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2$vm">;
+
+// op vd, vs2 (use vs1 as instruction encoding)
+class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+ : RVInstV<funct6, vs1, opv, (outs VR:$vd),
+ (ins VR:$vs2), opcodestr,
+ "$vd, $vs2"> {
+ let vm = 1;
+}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
//===----------------------------------------------------------------------===//
@@ -1767,4 +1775,5 @@
}
} // Predicates = [HasVInstructionsI64, IsRV64]
+include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoVPseudos.td"
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -219,6 +219,13 @@
let PredicateMethod = "isImm";
}
+def uimm6 : Operand<XLenVT> {
+ let ParserMatchClass = UImmAsmOperand<6>;
+ let DecoderMethod = "decodeUImmOperand<6>";
+ let OperandType = "OPERAND_UIMM6";
+ let OperandNamespace = "RISCVOp";
+}
+
def uimm7_opcode : Operand<XLenVT> {
let ParserMatchClass = InsnDirectiveOpcode;
let DecoderMethod = "decodeUImmOperand<7>";
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1681,6 +1681,15 @@
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
break;
+ case RISCVOp::OPERAND_RVKRNUM_0_7:
+ Ok = Imm >= 0 && Imm <= 7;
+ break;
+ case RISCVOp::OPERAND_RVKRNUM_1_10:
+ Ok = Imm >= 1 && Imm <= 10;
+ break;
+ case RISCVOp::OPERAND_RVKRNUM_2_14:
+ Ok = Imm >= 2 && Imm <= 14;
+ break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -148,6 +148,7 @@
def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;
def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
+def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>;
def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
class RVInst<dag outs, dag ins, string opcodestr, string argstr,
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -465,6 +465,55 @@
// tuning CPU names.
def Feature32Bit
: SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
+
+def FeatureStdExtZvkb
+ : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+ "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkb),
+ "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+
+def FeatureStdExtZvkg
+ : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
+ "'Zvkg' (Vector GCM instructions for Cryptography.)">;
+def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkg),
+ "'Zvkg' (Vector GCM instructions for Cryptography.)">;
+
+def FeatureStdExtZvknha
+ : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
+ "'Zvknha' (Vector SHA-2. (SHA-256 only))">;
+
+def FeatureStdExtZvknhb
+ : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+ "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))",
+ [FeatureStdExtZvknha]>;
+def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),
+ "'Zvknha' (Vector SHA-2. (SHA-256 only)) or "
+ "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))">;
+
+def FeatureStdExtZvkns
+ : SubtargetFeature<"experimental-zvkns", "HasStdExtZvkns", "true",
+ "'Zvkns' (Vector AES Encryption & Decryption (Single Round))">;
+def HasStdExtZvkns : Predicate<"Subtarget->hasStdExtZvkns()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkns),
+ "'Zvkns' (Vector AES Encryption & Decryption (Single Round))">;
+
+def FeatureStdExtZvksed
+ : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
+ "'Zvksed' (SM4 Block Cipher Instructions.)">;
+def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvksed),
+ "'Zvksed' (SM4 Block Cipher Instructions.)">;
+
+def FeatureStdExtZvksh
+ : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
+ "'Zvksh' (SM3 Hash Function Instructions.)">;
+def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvksh),
+ "'Zvksh' (SM3 Hash Function Instructions.)">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -237,6 +237,7 @@
OPERAND_UIMM3,
OPERAND_UIMM4,
OPERAND_UIMM5,
+ OPERAND_UIMM6,
OPERAND_UIMM7,
OPERAND_UIMM7_LSB00,
OPERAND_UIMM8_LSB00,
@@ -257,7 +258,10 @@
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
OPERAND_RVKRNUM,
- OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
+ OPERAND_RVKRNUM_0_7,
+ OPERAND_RVKRNUM_1_10,
+ OPERAND_RVKRNUM_2_14,
+ OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -571,6 +571,7 @@
bool isUImm2() { return IsUImm<2>(); }
bool isUImm3() { return IsUImm<3>(); }
bool isUImm5() { return IsUImm<5>(); }
+ bool isUImm6() { return IsUImm<6>(); }
bool isUImm7() { return IsUImm<7>(); }
bool isRnumArg() const {
@@ -583,6 +584,36 @@
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isRnumArg_0_7() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(7) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
+ bool isRnumArg_1_10() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && Imm >= INT64_C(1) && Imm <= INT64_C(10) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
+ bool isRnumArg_2_14() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && Imm >= INT64_C(2) && Imm <= INT64_C(14) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isSImm5() const {
if (!isImm())
return false;
@@ -1286,6 +1317,15 @@
case Match_InvalidRnumArg: {
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
}
+ case Match_InvalidRnumArg_0_7: {
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 7);
+ }
+ case Match_InvalidRnumArg_1_10: {
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 1, 10);
+ }
+ case Match_InvalidRnumArg_2_14: {
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 2, 14);
+ }
}
llvm_unreachable("Unknown match type detected!");
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -118,6 +118,15 @@
{"zvfh", RISCVExtensionVersion{0, 1}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
+
+ // vector crypto
+ {"zvkb", RISCVExtensionVersion{0, 1}},
+ {"zvkg", RISCVExtensionVersion{0, 1}},
+ {"zvknha", RISCVExtensionVersion{0, 1}},
+ {"zvknhb", RISCVExtensionVersion{0, 1}},
+ {"zvkns", RISCVExtensionVersion{0, 1}},
+ {"zvksed", RISCVExtensionVersion{0, 1}},
+ {"zvksh", RISCVExtensionVersion{0, 1}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -753,6 +762,17 @@
errc::invalid_argument,
"zvl*b requires v or zve* extension to also be specified");
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvknha") || Exts.count("zvkns") ||
+ Exts.count("zvksed") || Exts.count("zvksh")) && !HasVector)
+ return createStringError(
+ errc::invalid_argument,
+ "zvk* requires v or zve* extension to also be specified");
+
+ if (Exts.count("zvknhb") && !Exts.count("zve64x"))
+ return createStringError(
+ errc::invalid_argument,
+ "zvknhb requires zve64x extension to also be specified");
+
// Additional dependency checks.
// TODO: The 'q' extension requires rv64.
// TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -145,6 +145,9 @@
``experimental-zvfh``
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
+``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvksed``, ``experimental-zvksh``
+ LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20221118/riscv-crypto-spec-vector_20221118.pdf>`_. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Vendor Extensions
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -46,6 +46,13 @@
// CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf
+// CHECK-NOT: __riscv_zvkb
+// CHECK-NOT: __riscv_zvkg
+// CHECK-NOT: __riscv_zvknha
+// CHECK-NOT: __riscv_zvknhb
+// CHECK-NOT: __riscv_zvkns
+// CHECK-NOT: __riscv_zvksed
+// CHECK-NOT: __riscv_zvksh
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -466,3 +473,59 @@
// RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \
// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 70000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvkb0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvkb0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// CHECK-ZVKB-EXT: __riscv_zvkb 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkg0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvkg0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// CHECK-ZVKG-EXT: __riscv_zvkg 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvknha0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvknha0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvknhb0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvknhb0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkns0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvkns0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNS-EXT %s
+// CHECK-ZVKNS-EXT: __riscv_zvkns 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvksed0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvksed0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// CHECK-ZVKSED-EXT: __riscv_zvksed 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvksh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvksh0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// CHECK-ZVKSH-EXT: __riscv_zvksh 1000{{$}}
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
