eopXD created this revision. eopXD added reviewers: craig.topper, kito-cheng, rogfer01, frasercrmck. Herald added subscribers: s.egerton, simoncook. Herald added a project: All. eopXD requested review of this revision. Herald added subscribers: cfe-commits, pcwang-thead. Herald added a project: clang.
Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D142094 Files: clang/docs/ReleaseNotes.rst Index: clang/docs/ReleaseNotes.rst =================================================================== --- clang/docs/ReleaseNotes.rst +++ clang/docs/ReleaseNotes.rst @@ -806,6 +806,17 @@ - Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the architecture extension union of ``-mcpu`` and ``-march`` before, and now will take architecture extensions from ``-march`` if both are given. +- An overall simplification of the RISC-V Vector intrinsics are done. The + simplification is based on + `riscv-non-isa/rvv-intrinsic-doc#186 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/186>`_. +- Intrinsics of `vcompress` and `vmerge` have been adjusted to have interfaces + be aligned among `vvm`, `vxm` intrinsics. The adjustment is base on + `riscv-non-isa/rvv-intrinsic-doc#185 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/185>`_. +- All RISC-V Vector intrinsics now share a `__riscv_` prefix, based on the + naming convention defined by + `riscv-non-isa/riscv-c-api-doc#31 <https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31>`_. +- Note that the RISC-V Vector C intrinsics are still under experiment. The RVV + C Intrinsic Task Group is working towards a ratified v1.0. X86 Support in Clang --------------------
Index: clang/docs/ReleaseNotes.rst =================================================================== --- clang/docs/ReleaseNotes.rst +++ clang/docs/ReleaseNotes.rst @@ -806,6 +806,17 @@ - Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the architecture extension union of ``-mcpu`` and ``-march`` before, and now will take architecture extensions from ``-march`` if both are given. +- An overall simplification of the RISC-V Vector intrinsics are done. The + simplification is based on + `riscv-non-isa/rvv-intrinsic-doc#186 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/186>`_. +- Intrinsics of `vcompress` and `vmerge` have been adjusted to have interfaces + be aligned among `vvm`, `vxm` intrinsics. The adjustment is base on + `riscv-non-isa/rvv-intrinsic-doc#185 <https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/185>`_. +- All RISC-V Vector intrinsics now share a `__riscv_` prefix, based on the + naming convention defined by + `riscv-non-isa/riscv-c-api-doc#31 <https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31>`_. +- Note that the RISC-V Vector C intrinsics are still under experiment. The RVV + C Intrinsic Task Group is working towards a ratified v1.0. X86 Support in Clang --------------------
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