philipp.tomsich created this revision.
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The Ampere1A core improves on the Ampere1 with key differences being:
- FEAT_MTE is now supported
- adds a new fusion pair for (A+B+1 and A-B-1)
Depends on D142395 <https://reviews.llvm.org/D142395>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D142396
Files:
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/TargetParser/Host.cpp
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/neon-dot-product.ll
llvm/test/CodeGen/AArch64/remat.ll
llvm/test/MC/AArch64/armv8.2a-dotprod.s
llvm/test/MC/AArch64/armv8.3a-rcpc.s
llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/unittests/TargetParser/Host.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===================================================================
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1341,6 +1341,15 @@
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM |
AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_RAND,
"8.6-A"),
+ ARMCPUTestParams("ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_FP16 |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+ AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM |
+ AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_RAND |
+ AArch64::AEK_MTE,
+ "8.6-A"),
ARMCPUTestParams(
"neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1403,7 +1412,7 @@
"8.2-A")));
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
Index: llvm/unittests/TargetParser/Host.cpp
===================================================================
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
"CPU part : 0xac3"),
"ampere1");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+ "CPU part : 0xac4"),
+ "ampere1a");
// MSM8992/4 weirdness
StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===================================================================
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
# CHECK: ldaprb w0, [x0]
# CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===================================================================
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===================================================================
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -14,6 +14,7 @@
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
@@ -39,6 +40,8 @@
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1 -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1a -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
udot v0.2s, v1.8b, v2.8b
sdot v0.2s, v1.8b, v2.8b
Index: llvm/test/CodeGen/AArch64/remat.ll
===================================================================
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -25,6 +25,7 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1a -o - %s | FileCheck %s
%X = type { i64, i64, i64 }
declare void @f(ptr)
Index: llvm/test/CodeGen/AArch64/neon-dot-product.ll
===================================================================
--- llvm/test/CodeGen/AArch64/neon-dot-product.ll
+++ llvm/test/CodeGen/AArch64/neon-dot-product.ll
@@ -6,6 +6,7 @@
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1 < %s | FileCheck %s
+; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1a < %s | FileCheck %s
declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
Index: llvm/test/CodeGen/AArch64/cpus.ll
===================================================================
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -36,6 +36,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
; CHECK-NOT: {{.*}} is not a recognized processor for this target
Index: llvm/lib/TargetParser/Host.cpp
===================================================================
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -309,6 +309,7 @@
if (Implementer == "0xc0") { // Ampere Computing
return StringSwitch<const char *>(Part)
.Case("0xac3", "ampere1")
+ .Case("0xac4", "ampere1a")
.Default("generic");
}
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -41,6 +41,7 @@
Others,
A64FX,
Ampere1,
+ Ampere1A,
AppleA7,
AppleA10,
AppleA11,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -276,6 +276,7 @@
MinVectorRegisterBitWidth = 128;
break;
case Ampere1:
+ case Ampere1A:
CacheLineSize = 64;
PrefFunctionLogAlignment = 6;
PrefLoopLogAlignment = 6;
Index: llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -379,6 +379,49 @@
return false;
}
+// "A + B + 1" or "A - B - 1"
+static bool isAddSub2RegAndConstOnePair(const MachineInstr *FirstMI,
+ const MachineInstr &SecondMI) {
+ int polarity = 1;
+
+ switch (SecondMI.getOpcode()) {
+ case AArch64::SUBWri:
+ case AArch64::SUBXri:
+ polarity = -1;
+ // fallthrough
+ case AArch64::ADDWri:
+ case AArch64::ADDXri:
+ if (!SecondMI.getOperand(2).isImm() || SecondMI.getOperand(2).getImm() != polarity)
+ return false;
+
+ // Assume the 1st instr to be a wildcard if it is unspecified.
+ if (FirstMI == nullptr) {
+ return true;
+ }
+ break;
+
+ default:
+ return false;
+ }
+
+ switch (FirstMI->getOpcode()) {
+ case AArch64::SUBWrr:
+ case AArch64::SUBXrr:
+ if (polarity == -1)
+ return true;
+ break;
+
+ case AArch64::ADDWrr:
+ case AArch64::ADDXrr:
+ if (polarity == 1)
+ return true;
+ break;
+ }
+
+
+ return false;
+}
+
/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
/// together. Given SecondMI, when FirstMI is unspecified, then check if
/// SecondMI may be part of a fused pair at all.
@@ -411,6 +454,8 @@
return true;
if (ST.hasFuseArithmeticLogic() && isArithmeticLogicPair(FirstMI, SecondMI))
return true;
+ if (ST.hasFuseeAddSub2RegAndConstOne() && isAddSub2RegAndConstOnePair(FirstMI, SecondMI))
+ return true;
return false;
}
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -289,6 +289,10 @@
"fuse-literals", "HasFuseLiterals", "true",
"CPU fuses literal generation operations">;
+def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<
+ "fuse-addsub-2reg-const1", "HasFuseeAddSub2RegAndConstOne", "true",
+ "CPU fuses (a + b + 1) and (a - b - 1)">;
+
def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
"Disable latency scheduling heuristic">;
@@ -1162,6 +1166,18 @@
FeatureFuseAddress,
FeatureFuseLiterals]>;
+def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
+ "Ampere Computing Ampere-1 processors", [
+ FeaturePostRAScheduler,
+ FeatureFuseAES,
+ FeatureLSLFast,
+ FeatureAggressiveFMA,
+ FeatureArithmeticBccFusion,
+ FeatureCmpBccFusion,
+ FeatureFuseAddress,
+ FeatureFuseLiterals,
+ FeatureFuseAddSub2RegAndConstOne]>;
+
def ProcessorFeatures {
list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
@@ -1295,6 +1311,9 @@
FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureSSBS, FeatureRandGen, FeatureSB];
+ list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
+ FeatureMTE, FeatureSSBS, FeatureRandGen,
+ FeatureSB];
// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
@@ -1450,6 +1469,9 @@
def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
[TuneAmpere1]>;
+def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
+ [TuneAmpere1A]>;
+
//===----------------------------------------------------------------------===//
// Assembly parser
//===----------------------------------------------------------------------===//
Index: llvm/include/llvm/TargetParser/AArch64TargetParser.h
===================================================================
--- llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -471,7 +471,11 @@
{"a64fx", ARMV8_2A, (AArch64::AEK_FP16 | AArch64::AEK_SVE)},
{"carmel", ARMV8_2A, (AArch64::AEK_FP16)},
{"ampere1", ARMV8_6A,
- (AArch64::AEK_FP16 | AArch64::AEK_SB | AArch64::AEK_RAND | AArch64::AEK_SSBS)},
+ (AArch64::AEK_FP16 | AArch64::AEK_RAND | AArch64::AEK_SSBS)},
+ {"ampere1a", ARMV8_6A,
+ (AArch64::AEK_FP16 | AArch64::AEK_RAND | AArch64::AEK_SM4 | AArch64::AEK_SHA3 |
+ AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_MTE |
+ AArch64::AEK_SB | AArch64::AEK_SSBS)},
// Invalid CPU
{"invalid", INVALID, (AArch64::AEK_INVALID)},
};
Index: clang/test/Misc/target-invalid-cpu-note.c
===================================================================
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}}
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
+// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, grace{{$}}
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
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