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Issue: When processing a f16 type value, a f16 value is extended to f32 after
load and processed in f32 form, and truncated back to f16 before store, even
when the target has zfh extension, which indicates the target has native half
type float support, and such kind of extend/truncate actions are not necessary.
Some changes:
1.Set native half type to legal when has zfh extension, which prevent
unnecessary promotion from f16 to f32, and unpromotion back to f16.
2.Add related test case to test generation of half type float.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149401
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/test/CodeGen/RISCV/_Float16-add.c
Index: clang/test/CodeGen/RISCV/_Float16-add.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/_Float16-add.c
@@ -0,0 +1,19 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zfh -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+_Float16 x;
+_Float16 y;
+_Float16 z;
+// CHECK-LABEL: @func(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr @z, align 2
+// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// CHECK-NEXT: store half [[ADD]], ptr @x, align 2
+// CHECK-NEXT: ret void
+//
+void func()
+{
+ x = y + z;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -349,6 +349,11 @@
ISAInfo = std::move(*ParseResult);
}
+ // Turn on native half type support by set half type to legal.
+ if (ISAInfo->hasExtension("zfh")){
+ HasLegalHalfType = true;
+ }
+
if (ABI.empty())
ABI = ISAInfo->computeDefaultABI().str();
Index: clang/test/CodeGen/RISCV/_Float16-add.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/_Float16-add.c
@@ -0,0 +1,19 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zfh -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+_Float16 x;
+_Float16 y;
+_Float16 z;
+// CHECK-LABEL: @func(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr @z, align 2
+// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// CHECK-NEXT: store half [[ADD]], ptr @x, align 2
+// CHECK-NEXT: ret void
+//
+void func()
+{
+ x = y + z;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -349,6 +349,11 @@
ISAInfo = std::move(*ParseResult);
}
+ // Turn on native half type support by set half type to legal.
+ if (ISAInfo->hasExtension("zfh")){
+ HasLegalHalfType = true;
+ }
+
if (ABI.empty())
ABI = ISAInfo->computeDefaultABI().str();
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