This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4134f836103e: [clang-format] Recognize Verilog type dimension in module header (authored by sstwcw).
Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149352/new/ https://reviews.llvm.org/D149352 Files: clang/lib/Format/TokenAnnotator.cpp clang/unittests/Format/FormatTestVerilog.cpp clang/unittests/Format/TokenAnnotatorTest.cpp Index: clang/unittests/Format/TokenAnnotatorTest.cpp =================================================================== --- clang/unittests/Format/TokenAnnotatorTest.cpp +++ clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1615,6 +1615,13 @@ Tokens = Annotate("extern function [1 : 0] x;"); ASSERT_EQ(Tokens.size(), 10u) << Tokens; EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon); + Tokens = Annotate("module test\n" + " (input wire [7 : 0] a[7 : 0]);\n" + "endmodule"); + ASSERT_EQ(Tokens.size(), 20u) << Tokens; + EXPECT_TOKEN(Tokens[4], tok::identifier, TT_VerilogDimensionedTypeName); + EXPECT_TOKEN(Tokens[7], tok::colon, TT_BitFieldColon); + EXPECT_TOKEN(Tokens[13], tok::colon, TT_BitFieldColon); // Test case labels and ternary operators. Tokens = Annotate("case (x)\n" " x:\n" Index: clang/unittests/Format/FormatTestVerilog.cpp =================================================================== --- clang/unittests/Format/FormatTestVerilog.cpp +++ clang/unittests/Format/FormatTestVerilog.cpp @@ -359,6 +359,12 @@ " input var shortreal in2,\n" " output tagged_st out);\n" "endmodule"); + // There should be a space following the type but not the variable name. + verifyFormat("module test\n" + " (input wire [7 : 0] a,\n" + " input wire b[7 : 0],\n" + " input wire [7 : 0] c[7 : 0]);\n" + "endmodule"); // Ports should be grouped by types. verifyFormat("module test\n" " (input [7 : 0] a,\n" Index: clang/lib/Format/TokenAnnotator.cpp =================================================================== --- clang/lib/Format/TokenAnnotator.cpp +++ clang/lib/Format/TokenAnnotator.cpp @@ -2165,6 +2165,10 @@ /// This is a heuristic based on whether \p Tok is an identifier following /// something that is likely a type. bool isStartOfName(const FormatToken &Tok) { + // Handled in ExpressionParser for Verilog. + if (Style.isVerilog()) + return false; + if (Tok.isNot(tok::identifier) || !Tok.Previous) return false;
Index: clang/unittests/Format/TokenAnnotatorTest.cpp =================================================================== --- clang/unittests/Format/TokenAnnotatorTest.cpp +++ clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1615,6 +1615,13 @@ Tokens = Annotate("extern function [1 : 0] x;"); ASSERT_EQ(Tokens.size(), 10u) << Tokens; EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon); + Tokens = Annotate("module test\n" + " (input wire [7 : 0] a[7 : 0]);\n" + "endmodule"); + ASSERT_EQ(Tokens.size(), 20u) << Tokens; + EXPECT_TOKEN(Tokens[4], tok::identifier, TT_VerilogDimensionedTypeName); + EXPECT_TOKEN(Tokens[7], tok::colon, TT_BitFieldColon); + EXPECT_TOKEN(Tokens[13], tok::colon, TT_BitFieldColon); // Test case labels and ternary operators. Tokens = Annotate("case (x)\n" " x:\n" Index: clang/unittests/Format/FormatTestVerilog.cpp =================================================================== --- clang/unittests/Format/FormatTestVerilog.cpp +++ clang/unittests/Format/FormatTestVerilog.cpp @@ -359,6 +359,12 @@ " input var shortreal in2,\n" " output tagged_st out);\n" "endmodule"); + // There should be a space following the type but not the variable name. + verifyFormat("module test\n" + " (input wire [7 : 0] a,\n" + " input wire b[7 : 0],\n" + " input wire [7 : 0] c[7 : 0]);\n" + "endmodule"); // Ports should be grouped by types. verifyFormat("module test\n" " (input [7 : 0] a,\n" Index: clang/lib/Format/TokenAnnotator.cpp =================================================================== --- clang/lib/Format/TokenAnnotator.cpp +++ clang/lib/Format/TokenAnnotator.cpp @@ -2165,6 +2165,10 @@ /// This is a heuristic based on whether \p Tok is an identifier following /// something that is likely a type. bool isStartOfName(const FormatToken &Tok) { + // Handled in ExpressionParser for Verilog. + if (Style.isVerilog()) + return false; + if (Tok.isNot(tok::identifier) || !Tok.Previous) return false;
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