eopXD updated this revision to Diff 528135.
eopXD added a comment.
Bump CI.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152070/new/
https://reviews.llvm.org/D152070
Files:
clang/include/clang/Basic/RISCVVTypes.def
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -156,6 +156,24 @@
}
}
+static VectorTypeModifier getTupleVTM(unsigned NF) {
+ switch(NF) {
+ case 2: return VectorTypeModifier::Tuple2;
+ case 3: return VectorTypeModifier::Tuple3;
+ case 4:
+ return VectorTypeModifier::Tuple4;
+ case 5:
+ return VectorTypeModifier::Tuple5;
+ case 6:
+ return VectorTypeModifier::Tuple6;
+ case 7:
+ return VectorTypeModifier::Tuple7;
+ case 8:
+ return VectorTypeModifier::Tuple8;
+ }
+ llvm_unreachable("2 <= NF <= 8");
+}
+
void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
if (!RVVI->getIRName().empty())
OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
@@ -364,15 +382,19 @@
TypeModifier::UnsignedInteger));
printType(*UT);
}
- // FIXME: Expand more type declaration
- if (I == 'i' && Log2LMUL == 0) { // vint32m1x2_t
+ for (int NF = 2; NF <= 8; ++NF) {
auto TupleT = TypeCache.computeType(
BT, Log2LMUL,
- PrototypeDescriptor(BaseTypeModifier::Vector,
- VectorTypeModifier::Tuple2,
+ PrototypeDescriptor(BaseTypeModifier::Vector, getTupleVTM(NF),
TypeModifier::SignedInteger));
+ auto TupleUT = TypeCache.computeType(
+ BT, Log2LMUL,
+ PrototypeDescriptor(BaseTypeModifier::Vector, getTupleVTM(NF),
+ TypeModifier::UnsignedInteger));
if (TupleT)
printType(*TupleT);
+ if (TupleUT)
+ printType(*TupleUT);
}
}
}
@@ -383,6 +405,14 @@
auto T = TypeCache.computeType(BT, Log2LMUL, PrototypeDescriptor::Vector);
if (T)
printType(*T);
+ for (int NF = 2; NF <= 8; ++NF) {
+ auto TupleT = TypeCache.computeType(
+ BT, Log2LMUL,
+ PrototypeDescriptor(BaseTypeModifier::Vector, getTupleVTM(NF),
+ TypeModifier::Float));
+ if (TupleT)
+ printType(*TupleT);
+ }
}
}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
@@ -72,7 +72,232 @@
// CHECK-NEXT: [[F64M2:%.*]] = alloca <vscale x 2 x double>, align 8
// CHECK-NEXT: [[F64M4:%.*]] = alloca <vscale x 4 x double>, align 8
// CHECK-NEXT: [[F64M8:%.*]] = alloca <vscale x 8 x double>, align 8
+// CHECK-NEXT: [[I8MF8X2:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X3:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X4:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X5:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X6:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X7:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF8X8:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X2:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X3:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X4:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X5:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X6:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X7:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF4X8:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X2:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X3:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X4:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X5:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X6:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X7:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8MF2X8:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X2:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X3:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X4:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X5:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X6:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X7:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M1X8:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[I8M2X2:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[I8M2X3:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[I8M2X4:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[I8M4X2:%.*]] = alloca { <vscale x 32 x i8>, <vscale x 32 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X2:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X3:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X4:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X5:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X6:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X7:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF8X8:%.*]] = alloca { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X2:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X3:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X4:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X5:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X6:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X7:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF4X8:%.*]] = alloca { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X2:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X3:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X4:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X5:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X6:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X7:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8MF2X8:%.*]] = alloca { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X2:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X3:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X4:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X5:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X6:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X7:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M1X8:%.*]] = alloca { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> }, align 1
+// CHECK-NEXT: [[U8M2X2:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[U8M2X3:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[U8M2X4:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 1
+// CHECK-NEXT: [[U8M4X2:%.*]] = alloca { <vscale x 32 x i8>, <vscale x 32 x i8> }, align 1
+// CHECK-NEXT: [[I16MF4X2:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X3:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X4:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X5:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X6:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X7:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF4X8:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X2:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X3:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X4:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X5:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X6:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X7:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16MF2X8:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X2:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X3:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X4:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X5:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X6:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X7:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M1X8:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[I16M2X2:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[I16M2X3:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[I16M2X4:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[I16M4X2:%.*]] = alloca { <vscale x 16 x i16>, <vscale x 16 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X2:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X3:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X4:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X5:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X6:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X7:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF4X8:%.*]] = alloca { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X2:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X3:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X4:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X5:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X6:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X7:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16MF2X8:%.*]] = alloca { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X2:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X3:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X4:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X5:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X6:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X7:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M1X8:%.*]] = alloca { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> }, align 2
+// CHECK-NEXT: [[U16M2X2:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[U16M2X3:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[U16M2X4:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 2
+// CHECK-NEXT: [[U16M4X2:%.*]] = alloca { <vscale x 16 x i16>, <vscale x 16 x i16> }, align 2
+// CHECK-NEXT: [[I32MF2X2:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X3:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X4:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X5:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X6:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X7:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[I32MF2X8:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
// CHECK-NEXT: [[I32M1X2:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X3:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X4:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X5:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X6:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X7:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M1X8:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[I32M2X2:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[I32M2X3:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[I32M2X4:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[I32M4X2:%.*]] = alloca { <vscale x 8 x i32>, <vscale x 8 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X2:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X3:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X4:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X5:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X6:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X7:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32MF2X8:%.*]] = alloca { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X2:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X3:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X4:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X5:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X6:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X7:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M1X8:%.*]] = alloca { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> }, align 4
+// CHECK-NEXT: [[U32M2X2:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[U32M2X3:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[U32M2X4:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 4
+// CHECK-NEXT: [[U32M4X2:%.*]] = alloca { <vscale x 8 x i32>, <vscale x 8 x i32> }, align 4
+// CHECK-NEXT: [[I64M1X2:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X3:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X4:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X5:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X6:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X7:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M1X8:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[I64M2X2:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[I64M2X3:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[I64M2X4:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[I64M4X2:%.*]] = alloca { <vscale x 4 x i64>, <vscale x 4 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X2:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X3:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X4:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X5:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X6:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X7:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M1X8:%.*]] = alloca { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> }, align 8
+// CHECK-NEXT: [[U64M2X2:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[U64M2X3:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[U64M2X4:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 8
+// CHECK-NEXT: [[U64M4X2:%.*]] = alloca { <vscale x 4 x i64>, <vscale x 4 x i64> }, align 8
+// CHECK-NEXT: [[F16MF4X2:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X3:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X4:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X5:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X6:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X7:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF4X8:%.*]] = alloca { <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X2:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X3:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X4:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X5:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X6:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X7:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16MF2X8:%.*]] = alloca { <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half> }, align 2
+// CHECK-NEXT: [[F16M1X2:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X3:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X4:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X5:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X6:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X7:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M1X8:%.*]] = alloca { <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half> }, align 2
+// CHECK-NEXT: [[F16M2X2:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 2
+// CHECK-NEXT: [[F16M2X3:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 2
+// CHECK-NEXT: [[F16M2X4:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 2
+// CHECK-NEXT: [[F16M4X2:%.*]] = alloca { <vscale x 16 x half>, <vscale x 16 x half> }, align 2
+// CHECK-NEXT: [[F32MF2X2:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X3:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X4:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X5:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X6:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X7:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32MF2X8:%.*]] = alloca { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> }, align 4
+// CHECK-NEXT: [[F32M1X2:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X3:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X4:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X5:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X6:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X7:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M1X8:%.*]] = alloca { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> }, align 4
+// CHECK-NEXT: [[F32M2X2:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 4
+// CHECK-NEXT: [[F32M2X3:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 4
+// CHECK-NEXT: [[F32M2X4:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 4
+// CHECK-NEXT: [[F32M4X2:%.*]] = alloca { <vscale x 8 x float>, <vscale x 8 x float> }, align 4
+// CHECK-NEXT: [[F64M1X2:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X3:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X4:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X5:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X6:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X7:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M1X8:%.*]] = alloca { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> }, align 8
+// CHECK-NEXT: [[F64M2X2:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 8
+// CHECK-NEXT: [[F64M2X3:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 8
+// CHECK-NEXT: [[F64M2X4:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 8
+// CHECK-NEXT: [[F64M4X2:%.*]] = alloca { <vscale x 4 x double>, <vscale x 4 x double> }, align 8
// CHECK-NEXT: ret void
//
void foo () {
@@ -151,5 +376,278 @@
vfloat64m4_t f64m4;
vfloat64m8_t f64m8;
+ // i8
+ vint8mf8x2_t i8mf8x2;
+ vint8mf8x3_t i8mf8x3;
+ vint8mf8x4_t i8mf8x4;
+ vint8mf8x5_t i8mf8x5;
+ vint8mf8x6_t i8mf8x6;
+ vint8mf8x7_t i8mf8x7;
+ vint8mf8x8_t i8mf8x8;
+
+ vint8mf4x2_t i8mf4x2;
+ vint8mf4x3_t i8mf4x3;
+ vint8mf4x4_t i8mf4x4;
+ vint8mf4x5_t i8mf4x5;
+ vint8mf4x6_t i8mf4x6;
+ vint8mf4x7_t i8mf4x7;
+ vint8mf4x8_t i8mf4x8;
+
+ vint8mf2x2_t i8mf2x2;
+ vint8mf2x3_t i8mf2x3;
+ vint8mf2x4_t i8mf2x4;
+ vint8mf2x5_t i8mf2x5;
+ vint8mf2x6_t i8mf2x6;
+ vint8mf2x7_t i8mf2x7;
+ vint8mf2x8_t i8mf2x8;
+
+ vint8m1x2_t i8m1x2;
+ vint8m1x3_t i8m1x3;
+ vint8m1x4_t i8m1x4;
+ vint8m1x5_t i8m1x5;
+ vint8m1x6_t i8m1x6;
+ vint8m1x7_t i8m1x7;
+ vint8m1x8_t i8m1x8;
+
+ vint8m2x2_t i8m2x2;
+ vint8m2x3_t i8m2x3;
+ vint8m2x4_t i8m2x4;
+
+ vint8m4x2_t i8m4x2;
+ // u8
+ vuint8mf8x2_t u8mf8x2;
+ vuint8mf8x3_t u8mf8x3;
+ vuint8mf8x4_t u8mf8x4;
+ vuint8mf8x5_t u8mf8x5;
+ vuint8mf8x6_t u8mf8x6;
+ vuint8mf8x7_t u8mf8x7;
+ vuint8mf8x8_t u8mf8x8;
+
+ vuint8mf4x2_t u8mf4x2;
+ vuint8mf4x3_t u8mf4x3;
+ vuint8mf4x4_t u8mf4x4;
+ vuint8mf4x5_t u8mf4x5;
+ vuint8mf4x6_t u8mf4x6;
+ vuint8mf4x7_t u8mf4x7;
+ vuint8mf4x8_t u8mf4x8;
+
+ vuint8mf2x2_t u8mf2x2;
+ vuint8mf2x3_t u8mf2x3;
+ vuint8mf2x4_t u8mf2x4;
+ vuint8mf2x5_t u8mf2x5;
+ vuint8mf2x6_t u8mf2x6;
+ vuint8mf2x7_t u8mf2x7;
+ vuint8mf2x8_t u8mf2x8;
+
+ vuint8m1x2_t u8m1x2;
+ vuint8m1x3_t u8m1x3;
+ vuint8m1x4_t u8m1x4;
+ vuint8m1x5_t u8m1x5;
+ vuint8m1x6_t u8m1x6;
+ vuint8m1x7_t u8m1x7;
+ vuint8m1x8_t u8m1x8;
+
+ vuint8m2x2_t u8m2x2;
+ vuint8m2x3_t u8m2x3;
+ vuint8m2x4_t u8m2x4;
+
+ vuint8m4x2_t u8m4x2;
+ // i16
+ vint16mf4x2_t i16mf4x2;
+ vint16mf4x3_t i16mf4x3;
+ vint16mf4x4_t i16mf4x4;
+ vint16mf4x5_t i16mf4x5;
+ vint16mf4x6_t i16mf4x6;
+ vint16mf4x7_t i16mf4x7;
+ vint16mf4x8_t i16mf4x8;
+
+ vint16mf2x2_t i16mf2x2;
+ vint16mf2x3_t i16mf2x3;
+ vint16mf2x4_t i16mf2x4;
+ vint16mf2x5_t i16mf2x5;
+ vint16mf2x6_t i16mf2x6;
+ vint16mf2x7_t i16mf2x7;
+ vint16mf2x8_t i16mf2x8;
+
+ vint16m1x2_t i16m1x2;
+ vint16m1x3_t i16m1x3;
+ vint16m1x4_t i16m1x4;
+ vint16m1x5_t i16m1x5;
+ vint16m1x6_t i16m1x6;
+ vint16m1x7_t i16m1x7;
+ vint16m1x8_t i16m1x8;
+
+ vint16m2x2_t i16m2x2;
+ vint16m2x3_t i16m2x3;
+ vint16m2x4_t i16m2x4;
+
+ vint16m4x2_t i16m4x2;
+ // u16
+ vuint16mf4x2_t u16mf4x2;
+ vuint16mf4x3_t u16mf4x3;
+ vuint16mf4x4_t u16mf4x4;
+ vuint16mf4x5_t u16mf4x5;
+ vuint16mf4x6_t u16mf4x6;
+ vuint16mf4x7_t u16mf4x7;
+ vuint16mf4x8_t u16mf4x8;
+
+ vuint16mf2x2_t u16mf2x2;
+ vuint16mf2x3_t u16mf2x3;
+ vuint16mf2x4_t u16mf2x4;
+ vuint16mf2x5_t u16mf2x5;
+ vuint16mf2x6_t u16mf2x6;
+ vuint16mf2x7_t u16mf2x7;
+ vuint16mf2x8_t u16mf2x8;
+
+ vuint16m1x2_t u16m1x2;
+ vuint16m1x3_t u16m1x3;
+ vuint16m1x4_t u16m1x4;
+ vuint16m1x5_t u16m1x5;
+ vuint16m1x6_t u16m1x6;
+ vuint16m1x7_t u16m1x7;
+ vuint16m1x8_t u16m1x8;
+
+ vuint16m2x2_t u16m2x2;
+ vuint16m2x3_t u16m2x3;
+ vuint16m2x4_t u16m2x4;
+
+ vuint16m4x2_t u16m4x2;
+ // i32
+ vint32mf2x2_t i32mf2x2;
+ vint32mf2x3_t i32mf2x3;
+ vint32mf2x4_t i32mf2x4;
+ vint32mf2x5_t i32mf2x5;
+ vint32mf2x6_t i32mf2x6;
+ vint32mf2x7_t i32mf2x7;
+ vint32mf2x8_t i32mf2x8;
+
vint32m1x2_t i32m1x2;
+ vint32m1x3_t i32m1x3;
+ vint32m1x4_t i32m1x4;
+ vint32m1x5_t i32m1x5;
+ vint32m1x6_t i32m1x6;
+ vint32m1x7_t i32m1x7;
+ vint32m1x8_t i32m1x8;
+
+ vint32m2x2_t i32m2x2;
+ vint32m2x3_t i32m2x3;
+ vint32m2x4_t i32m2x4;
+
+ vint32m4x2_t i32m4x2;
+ // u32
+ vuint32mf2x2_t u32mf2x2;
+ vuint32mf2x3_t u32mf2x3;
+ vuint32mf2x4_t u32mf2x4;
+ vuint32mf2x5_t u32mf2x5;
+ vuint32mf2x6_t u32mf2x6;
+ vuint32mf2x7_t u32mf2x7;
+ vuint32mf2x8_t u32mf2x8;
+
+ vuint32m1x2_t u32m1x2;
+ vuint32m1x3_t u32m1x3;
+ vuint32m1x4_t u32m1x4;
+ vuint32m1x5_t u32m1x5;
+ vuint32m1x6_t u32m1x6;
+ vuint32m1x7_t u32m1x7;
+ vuint32m1x8_t u32m1x8;
+
+ vuint32m2x2_t u32m2x2;
+ vuint32m2x3_t u32m2x3;
+ vuint32m2x4_t u32m2x4;
+
+ vuint32m4x2_t u32m4x2;
+ //i64
+ vint64m1x2_t i64m1x2;
+ vint64m1x3_t i64m1x3;
+ vint64m1x4_t i64m1x4;
+ vint64m1x5_t i64m1x5;
+ vint64m1x6_t i64m1x6;
+ vint64m1x7_t i64m1x7;
+ vint64m1x8_t i64m1x8;
+
+ vint64m2x2_t i64m2x2;
+ vint64m2x3_t i64m2x3;
+ vint64m2x4_t i64m2x4;
+
+ vint64m4x2_t i64m4x2;
+ // u64
+ vuint64m1x2_t u64m1x2;
+ vuint64m1x3_t u64m1x3;
+ vuint64m1x4_t u64m1x4;
+ vuint64m1x5_t u64m1x5;
+ vuint64m1x6_t u64m1x6;
+ vuint64m1x7_t u64m1x7;
+ vuint64m1x8_t u64m1x8;
+
+ vuint64m2x2_t u64m2x2;
+ vuint64m2x3_t u64m2x3;
+ vuint64m2x4_t u64m2x4;
+
+ vuint64m4x2_t u64m4x2;
+ // f16
+ vfloat16mf4x2_t f16mf4x2;
+ vfloat16mf4x3_t f16mf4x3;
+ vfloat16mf4x4_t f16mf4x4;
+ vfloat16mf4x5_t f16mf4x5;
+ vfloat16mf4x6_t f16mf4x6;
+ vfloat16mf4x7_t f16mf4x7;
+ vfloat16mf4x8_t f16mf4x8;
+
+ vfloat16mf2x2_t f16mf2x2;
+ vfloat16mf2x3_t f16mf2x3;
+ vfloat16mf2x4_t f16mf2x4;
+ vfloat16mf2x5_t f16mf2x5;
+ vfloat16mf2x6_t f16mf2x6;
+ vfloat16mf2x7_t f16mf2x7;
+ vfloat16mf2x8_t f16mf2x8;
+
+ vfloat16m1x2_t f16m1x2;
+ vfloat16m1x3_t f16m1x3;
+ vfloat16m1x4_t f16m1x4;
+ vfloat16m1x5_t f16m1x5;
+ vfloat16m1x6_t f16m1x6;
+ vfloat16m1x7_t f16m1x7;
+ vfloat16m1x8_t f16m1x8;
+
+ vfloat16m2x2_t f16m2x2;
+ vfloat16m2x3_t f16m2x3;
+ vfloat16m2x4_t f16m2x4;
+
+ vfloat16m4x2_t f16m4x2;
+ // f32
+ vfloat32mf2x2_t f32mf2x2;
+ vfloat32mf2x3_t f32mf2x3;
+ vfloat32mf2x4_t f32mf2x4;
+ vfloat32mf2x5_t f32mf2x5;
+ vfloat32mf2x6_t f32mf2x6;
+ vfloat32mf2x7_t f32mf2x7;
+ vfloat32mf2x8_t f32mf2x8;
+
+ vfloat32m1x2_t f32m1x2;
+ vfloat32m1x3_t f32m1x3;
+ vfloat32m1x4_t f32m1x4;
+ vfloat32m1x5_t f32m1x5;
+ vfloat32m1x6_t f32m1x6;
+ vfloat32m1x7_t f32m1x7;
+ vfloat32m1x8_t f32m1x8;
+
+ vfloat32m2x2_t f32m2x2;
+ vfloat32m2x3_t f32m2x3;
+ vfloat32m2x4_t f32m2x4;
+
+ vfloat32m4x2_t f32m4x2;
+ //i64
+ vfloat64m1x2_t f64m1x2;
+ vfloat64m1x3_t f64m1x3;
+ vfloat64m1x4_t f64m1x4;
+ vfloat64m1x5_t f64m1x5;
+ vfloat64m1x6_t f64m1x6;
+ vfloat64m1x7_t f64m1x7;
+ vfloat64m1x8_t f64m1x8;
+
+ vfloat64m2x2_t f64m2x2;
+ vfloat64m2x3_t f64m2x3;
+ vfloat64m2x4_t f64m2x4;
+
+ vfloat64m4x2_t f64m4x2;
}
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===================================================================
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -115,6 +115,8 @@
return false;
if (IsTuple && (NF == 1 || NF > 8))
return false;
+ if (IsTuple && (1 << std::max(0, LMUL.Log2LMUL)) * NF > 8)
+ return false;
unsigned V = *Scale;
switch (ElementBitwidth) {
case 1:
@@ -561,6 +563,24 @@
case 2:
VTM = VectorTypeModifier::Tuple2;
break;
+ case 3:
+ VTM = VectorTypeModifier::Tuple3;
+ break;
+ case 4:
+ VTM = VectorTypeModifier::Tuple4;
+ break;
+ case 5:
+ VTM = VectorTypeModifier::Tuple5;
+ break;
+ case 6:
+ VTM = VectorTypeModifier::Tuple6;
+ break;
+ case 7:
+ VTM = VectorTypeModifier::Tuple7;
+ break;
+ case 8:
+ VTM = VectorTypeModifier::Tuple8;
+ break;
default:
llvm_unreachable("Unhandled NF");
}
@@ -729,6 +749,36 @@
NF = 2;
break;
}
+ case VectorTypeModifier::Tuple3: {
+ IsTuple = true;
+ NF = 3;
+ break;
+ }
+ case VectorTypeModifier::Tuple4: {
+ IsTuple = true;
+ NF = 4;
+ break;
+ }
+ case VectorTypeModifier::Tuple5: {
+ IsTuple = true;
+ NF = 5;
+ break;
+ }
+ case VectorTypeModifier::Tuple6: {
+ IsTuple = true;
+ NF = 6;
+ break;
+ }
+ case VectorTypeModifier::Tuple7: {
+ IsTuple = true;
+ NF = 7;
+ break;
+ }
+ case VectorTypeModifier::Tuple8: {
+ IsTuple = true;
+ NF = 8;
+ break;
+ }
case VectorTypeModifier::NoModifier:
break;
}
@@ -815,10 +865,6 @@
std::optional<RVVTypes>
RVVTypeCache::computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
ArrayRef<PrototypeDescriptor> Prototype) {
- // LMUL x NF must be less than or equal to 8.
- if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8)
- return std::nullopt;
-
RVVTypes Types;
for (const PrototypeDescriptor &Proto : Prototype) {
auto T = computeType(BT, Log2LMUL, Proto);
@@ -994,8 +1040,7 @@
// If HasVL, append PrototypeDescriptor:VL to last operand
if (HasVL)
NewPrototype.push_back(PrototypeDescriptor::VL);
- if (IsTuple)
- NewPrototype[0].VTM = static_cast<uint8_t>(VectorTypeModifier::Tuple2);
+
return NewPrototype;
}
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===================================================================
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -59,6 +59,12 @@
SFixedLog2LMUL2,
SFixedLog2LMUL3,
Tuple2,
+ Tuple3,
+ Tuple4,
+ Tuple5,
+ Tuple6,
+ Tuple7,
+ Tuple8,
};
// Similar to basic type but used to describe what's kind of type related to
@@ -302,7 +308,7 @@
ScalarTypeKind getScalarType() const { return ScalarType; }
VScaleVal getScale() const { return Scale; }
unsigned getNF() const {
- assert(NF > 1 && NF < 8 && "Only legal NF should be fetched");
+ assert(NF > 1 && NF <= 8 && "Only legal NF should be fetched");
return NF;
}
Index: clang/include/clang/Basic/RISCVVTypes.def
===================================================================
--- clang/include/clang/Basic/RISCVVTypes.def
+++ clang/include/clang/Basic/RISCVVTypes.def
@@ -145,8 +145,282 @@
RVV_PREDICATE_TYPE("__rvv_bool64_t", RvvBool64, RvvBool64Ty, 1)
//===- Tuple vector types -------------------------------------------------===//
+//===- Int8 tuple types --------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x2_t", RvvInt8mf8x2, RvvInt8mf8x2Ty, 1, 8, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x3_t", RvvInt8mf8x3, RvvInt8mf8x3Ty, 1, 8, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x4_t", RvvInt8mf8x4, RvvInt8mf8x4Ty, 1, 8, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x5_t", RvvInt8mf8x5, RvvInt8mf8x5Ty, 1, 8, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x6_t", RvvInt8mf8x6, RvvInt8mf8x6Ty, 1, 8, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x7_t", RvvInt8mf8x7, RvvInt8mf8x7Ty, 1, 8, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8x8_t", RvvInt8mf8x8, RvvInt8mf8x8Ty, 1, 8, 8, true)
-RVV_VECTOR_TYPE_INT("__rvv_int32m1x2_t", RvvInt32m1x2, RvvInt32m1x2Ty, 2, 32, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x2_t", RvvInt8mf4x2, RvvInt8mf4x2Ty, 2, 8, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x3_t", RvvInt8mf4x3, RvvInt8mf4x3Ty, 2, 8, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x4_t", RvvInt8mf4x4, RvvInt8mf4x4Ty, 2, 8, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x5_t", RvvInt8mf4x5, RvvInt8mf4x5Ty, 2, 8, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x6_t", RvvInt8mf4x6, RvvInt8mf4x6Ty, 2, 8, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x7_t", RvvInt8mf4x7, RvvInt8mf4x7Ty, 2, 8, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4x8_t", RvvInt8mf4x8, RvvInt8mf4x8Ty, 2, 8, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x2_t", RvvInt8mf2x2, RvvInt8mf2x2Ty, 4, 8, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x3_t", RvvInt8mf2x3, RvvInt8mf2x3Ty, 4, 8, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x4_t", RvvInt8mf2x4, RvvInt8mf2x4Ty, 4, 8, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x5_t", RvvInt8mf2x5, RvvInt8mf2x5Ty, 4, 8, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x6_t", RvvInt8mf2x6, RvvInt8mf2x6Ty, 4, 8, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x7_t", RvvInt8mf2x7, RvvInt8mf2x7Ty, 4, 8, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2x8_t", RvvInt8mf2x8, RvvInt8mf2x8Ty, 4, 8, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x2_t", RvvInt8m1x2, RvvInt8m1x2Ty, 8, 8, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x3_t", RvvInt8m1x3, RvvInt8m1x3Ty, 8, 8, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x4_t", RvvInt8m1x4, RvvInt8m1x4Ty, 8, 8, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x5_t", RvvInt8m1x5, RvvInt8m1x5Ty, 8, 8, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x6_t", RvvInt8m1x6, RvvInt8m1x6Ty, 8, 8, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x7_t", RvvInt8m1x7, RvvInt8m1x7Ty, 8, 8, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1x8_t", RvvInt8m1x8, RvvInt8m1x8Ty, 8, 8, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int8m2x2_t", RvvInt8m2x2, RvvInt8m2x2Ty, 16, 8, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m2x3_t", RvvInt8m2x3, RvvInt8m2x3Ty, 16, 8, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m2x4_t", RvvInt8m2x4, RvvInt8m2x4Ty, 16, 8, 4, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int8m4x2_t", RvvInt8m4x2, RvvInt8m4x2Ty, 32, 8, 2, true)
+//===- Uint8 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x2_t", RvvUint8mf8x2, RvvUint8mf8x2Ty, 1, 8, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x3_t", RvvUint8mf8x3, RvvUint8mf8x3Ty, 1, 8, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x4_t", RvvUint8mf8x4, RvvUint8mf8x4Ty, 1, 8, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x5_t", RvvUint8mf8x5, RvvUint8mf8x5Ty, 1, 8, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x6_t", RvvUint8mf8x6, RvvUint8mf8x6Ty, 1, 8, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x7_t", RvvUint8mf8x7, RvvUint8mf8x7Ty, 1, 8, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8x8_t", RvvUint8mf8x8, RvvUint8mf8x8Ty, 1, 8, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x2_t", RvvUint8mf4x2, RvvUint8mf4x2Ty, 2, 8, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x3_t", RvvUint8mf4x3, RvvUint8mf4x3Ty, 2, 8, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x4_t", RvvUint8mf4x4, RvvUint8mf4x4Ty, 2, 8, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x5_t", RvvUint8mf4x5, RvvUint8mf4x5Ty, 2, 8, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x6_t", RvvUint8mf4x6, RvvUint8mf4x6Ty, 2, 8, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x7_t", RvvUint8mf4x7, RvvUint8mf4x7Ty, 2, 8, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4x8_t", RvvUint8mf4x8, RvvUint8mf4x8Ty, 2, 8, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x2_t", RvvUint8mf2x2, RvvUint8mf2x2Ty, 4, 8, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x3_t", RvvUint8mf2x3, RvvUint8mf2x3Ty, 4, 8, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x4_t", RvvUint8mf2x4, RvvUint8mf2x4Ty, 4, 8, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x5_t", RvvUint8mf2x5, RvvUint8mf2x5Ty, 4, 8, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x6_t", RvvUint8mf2x6, RvvUint8mf2x6Ty, 4, 8, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x7_t", RvvUint8mf2x7, RvvUint8mf2x7Ty, 4, 8, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2x8_t", RvvUint8mf2x8, RvvUint8mf2x8Ty, 4, 8, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x2_t", RvvUint8m1x2, RvvUint8m1x2Ty, 8, 8, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x3_t", RvvUint8m1x3, RvvUint8m1x3Ty, 8, 8, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x4_t", RvvUint8m1x4, RvvUint8m1x4Ty, 8, 8, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x5_t", RvvUint8m1x5, RvvUint8m1x5Ty, 8, 8, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x6_t", RvvUint8m1x6, RvvUint8m1x6Ty, 8, 8, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x7_t", RvvUint8m1x7, RvvUint8m1x7Ty, 8, 8, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1x8_t", RvvUint8m1x8, RvvUint8m1x8Ty, 8, 8, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8m2x2_t", RvvUint8m2x2, RvvUint8m2x2Ty, 16, 8, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m2x3_t", RvvUint8m2x3, RvvUint8m2x3Ty, 16, 8, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m2x4_t", RvvUint8m2x4, RvvUint8m2x4Ty, 16, 8, 4, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8m4x2_t", RvvUint8m4x2, RvvUint8m4x2Ty, 32, 8, 2, false)
+//===- Int16 tuple types --------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x2_t", RvvInt16mf4x2, RvvInt16mf4x2Ty, 1, 16, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x3_t", RvvInt16mf4x3, RvvInt16mf4x3Ty, 1, 16, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x4_t", RvvInt16mf4x4, RvvInt16mf4x4Ty, 1, 16, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x5_t", RvvInt16mf4x5, RvvInt16mf4x5Ty, 1, 16, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x6_t", RvvInt16mf4x6, RvvInt16mf4x6Ty, 1, 16, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x7_t", RvvInt16mf4x7, RvvInt16mf4x7Ty, 1, 16, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4x8_t", RvvInt16mf4x8, RvvInt16mf4x8Ty, 1, 16, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x2_t", RvvInt16mf2x2, RvvInt16mf2x2Ty, 2, 16, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x3_t", RvvInt16mf2x3, RvvInt16mf2x3Ty, 2, 16, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x4_t", RvvInt16mf2x4, RvvInt16mf2x4Ty, 2, 16, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x5_t", RvvInt16mf2x5, RvvInt16mf2x5Ty, 2, 16, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x6_t", RvvInt16mf2x6, RvvInt16mf2x6Ty, 2, 16, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x7_t", RvvInt16mf2x7, RvvInt16mf2x7Ty, 2, 16, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2x8_t", RvvInt16mf2x8, RvvInt16mf2x8Ty, 2, 16, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x2_t", RvvInt16m1x2, RvvInt16m1x2Ty, 4, 16, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x3_t", RvvInt16m1x3, RvvInt16m1x3Ty, 4, 16, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x4_t", RvvInt16m1x4, RvvInt16m1x4Ty, 4, 16, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x5_t", RvvInt16m1x5, RvvInt16m1x5Ty, 4, 16, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x6_t", RvvInt16m1x6, RvvInt16m1x6Ty, 4, 16, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x7_t", RvvInt16m1x7, RvvInt16m1x7Ty, 4, 16, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1x8_t", RvvInt16m1x8, RvvInt16m1x8Ty, 4, 16, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16m2x2_t", RvvInt16m2x2, RvvInt16m2x2Ty, 8, 16, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m2x3_t", RvvInt16m2x3, RvvInt16m2x3Ty, 8, 16, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m2x4_t", RvvInt16m2x4, RvvInt16m2x4Ty, 8, 16, 4, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16m4x2_t", RvvInt16m4x2, RvvInt16m4x2Ty, 16, 16, 2, true)
+//===- Uint16 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x2_t", RvvUint16mf4x2, RvvUint16mf4x2Ty, 1, 16, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x3_t", RvvUint16mf4x3, RvvUint16mf4x3Ty, 1, 16, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x4_t", RvvUint16mf4x4, RvvUint16mf4x4Ty, 1, 16, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x5_t", RvvUint16mf4x5, RvvUint16mf4x5Ty, 1, 16, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x6_t", RvvUint16mf4x6, RvvUint16mf4x6Ty, 1, 16, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x7_t", RvvUint16mf4x7, RvvUint16mf4x7Ty, 1, 16, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4x8_t", RvvUint16mf4x8, RvvUint16mf4x8Ty, 1, 16, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x2_t", RvvUint16mf2x2, RvvUint16mf2x2Ty, 2, 16, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x3_t", RvvUint16mf2x3, RvvUint16mf2x3Ty, 2, 16, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x4_t", RvvUint16mf2x4, RvvUint16mf2x4Ty, 2, 16, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x5_t", RvvUint16mf2x5, RvvUint16mf2x5Ty, 2, 16, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x6_t", RvvUint16mf2x6, RvvUint16mf2x6Ty, 2, 16, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x7_t", RvvUint16mf2x7, RvvUint16mf2x7Ty, 2, 16, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2x8_t", RvvUint16mf2x8, RvvUint16mf2x8Ty, 2, 16, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x2_t", RvvUint16m1x2, RvvUint16m1x2Ty, 4, 16, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x3_t", RvvUint16m1x3, RvvUint16m1x3Ty, 4, 16, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x4_t", RvvUint16m1x4, RvvUint16m1x4Ty, 4, 16, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x5_t", RvvUint16m1x5, RvvUint16m1x5Ty, 4, 16, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x6_t", RvvUint16m1x6, RvvUint16m1x6Ty, 4, 16, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x7_t", RvvUint16m1x7, RvvUint16m1x7Ty, 4, 16, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1x8_t", RvvUint16m1x8, RvvUint16m1x8Ty, 4, 16, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16m2x2_t", RvvUint16m2x2, RvvUint16m2x2Ty, 8, 16, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m2x3_t", RvvUint16m2x3, RvvUint16m2x3Ty, 8, 16, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m2x4_t", RvvUint16m2x4, RvvUint16m2x4Ty, 8, 16, 4, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16m4x2_t", RvvUint16m4x2, RvvUint16m4x2Ty, 16, 16, 2, false)
+//===- Int32 tuple types --------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x2_t", RvvInt32mf2x2, RvvInt32mf2x2Ty, 1, 32, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x3_t", RvvInt32mf2x3, RvvInt32mf2x3Ty, 1, 32, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x4_t", RvvInt32mf2x4, RvvInt32mf2x4Ty, 1, 32, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x5_t", RvvInt32mf2x5, RvvInt32mf2x5Ty, 1, 32, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x6_t", RvvInt32mf2x6, RvvInt32mf2x6Ty, 1, 32, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x7_t", RvvInt32mf2x7, RvvInt32mf2x7Ty, 1, 32, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2x8_t", RvvInt32mf2x8, RvvInt32mf2x8Ty, 1, 32, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x2_t", RvvInt32m1x2, RvvInt32m1x2Ty, 2, 32, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x3_t", RvvInt32m1x3, RvvInt32m1x3Ty, 2, 32, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x4_t", RvvInt32m1x4, RvvInt32m1x4Ty, 2, 32, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x5_t", RvvInt32m1x5, RvvInt32m1x5Ty, 2, 32, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x6_t", RvvInt32m1x6, RvvInt32m1x6Ty, 2, 32, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x7_t", RvvInt32m1x7, RvvInt32m1x7Ty, 2, 32, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1x8_t", RvvInt32m1x8, RvvInt32m1x8Ty, 2, 32, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int32m2x2_t", RvvInt32m2x2, RvvInt32m2x2Ty, 4, 32, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m2x3_t", RvvInt32m2x3, RvvInt32m2x3Ty, 4, 32, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m2x4_t", RvvInt32m2x4, RvvInt32m2x4Ty, 4, 32, 4, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int32m4x2_t", RvvInt32m4x2, RvvInt32m4x2Ty, 8, 32, 2, true)
+//===- Uint32 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x2_t", RvvUint32mf2x2, RvvUint32mf2x2Ty, 1, 32, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x3_t", RvvUint32mf2x3, RvvUint32mf2x3Ty, 1, 32, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x4_t", RvvUint32mf2x4, RvvUint32mf2x4Ty, 1, 32, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x5_t", RvvUint32mf2x5, RvvUint32mf2x5Ty, 1, 32, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x6_t", RvvUint32mf2x6, RvvUint32mf2x6Ty, 1, 32, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x7_t", RvvUint32mf2x7, RvvUint32mf2x7Ty, 1, 32, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2x8_t", RvvUint32mf2x8, RvvUint32mf2x8Ty, 1, 32, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x2_t", RvvUint32m1x2, RvvUint32m1x2Ty, 2, 32, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x3_t", RvvUint32m1x3, RvvUint32m1x3Ty, 2, 32, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x4_t", RvvUint32m1x4, RvvUint32m1x4Ty, 2, 32, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x5_t", RvvUint32m1x5, RvvUint32m1x5Ty, 2, 32, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x6_t", RvvUint32m1x6, RvvUint32m1x6Ty, 2, 32, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x7_t", RvvUint32m1x7, RvvUint32m1x7Ty, 2, 32, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1x8_t", RvvUint32m1x8, RvvUint32m1x8Ty, 2, 32, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint32m2x2_t", RvvUint32m2x2, RvvUint32m2x2Ty, 4, 32, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m2x3_t", RvvUint32m2x3, RvvUint32m2x3Ty, 4, 32, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m2x4_t", RvvUint32m2x4, RvvUint32m2x4Ty, 4, 32, 4, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint32m4x2_t", RvvUint32m4x2, RvvUint32m4x2Ty, 8, 32, 2, false)
+//===- Int64 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x2_t", RvvInt64m1x2, RvvInt64m1x2Ty, 1, 64, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x3_t", RvvInt64m1x3, RvvInt64m1x3Ty, 1, 64, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x4_t", RvvInt64m1x4, RvvInt64m1x4Ty, 1, 64, 4, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x5_t", RvvInt64m1x5, RvvInt64m1x5Ty, 1, 64, 5, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x6_t", RvvInt64m1x6, RvvInt64m1x6Ty, 1, 64, 6, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x7_t", RvvInt64m1x7, RvvInt64m1x7Ty, 1, 64, 7, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m1x8_t", RvvInt64m1x8, RvvInt64m1x8Ty, 1, 64, 8, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int64m2x2_t", RvvInt64m2x2, RvvInt64m2x2Ty, 2, 64, 2, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m2x3_t", RvvInt64m2x3, RvvInt64m2x3Ty, 2, 64, 3, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m2x4_t", RvvInt64m2x4, RvvInt64m2x4Ty, 2, 64, 4, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_int64m4x2_t", RvvInt64m4x2, RvvInt64m4x2Ty, 4, 64, 2, true)
+//===- Uint64 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x2_t", RvvUint64m1x2, RvvUint64m1x2Ty, 1, 64, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x3_t", RvvUint64m1x3, RvvUint64m1x3Ty, 1, 64, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x4_t", RvvUint64m1x4, RvvUint64m1x4Ty, 1, 64, 4, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x5_t", RvvUint64m1x5, RvvUint64m1x5Ty, 1, 64, 5, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x6_t", RvvUint64m1x6, RvvUint64m1x6Ty, 1, 64, 6, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x7_t", RvvUint64m1x7, RvvUint64m1x7Ty, 1, 64, 7, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1x8_t", RvvUint64m1x8, RvvUint64m1x8Ty, 1, 64, 8, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint64m2x2_t", RvvUint64m2x2, RvvUint64m2x2Ty, 2, 64, 2, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m2x3_t", RvvUint64m2x3, RvvUint64m2x3Ty, 2, 64, 3, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m2x4_t", RvvUint64m2x4, RvvUint64m2x4Ty, 2, 64, 4, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint64m4x2_t", RvvUint64m4x2, RvvUint64m4x2Ty, 4, 64, 2, false)
+//===- Float16 tuple types --------------------------------------------------===//
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x2_t", RvvFloat16mf4x2, RvvFloat16mf4x2Ty, 1, 16, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x3_t", RvvFloat16mf4x3, RvvFloat16mf4x3Ty, 1, 16, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x4_t", RvvFloat16mf4x4, RvvFloat16mf4x4Ty, 1, 16, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x5_t", RvvFloat16mf4x5, RvvFloat16mf4x5Ty, 1, 16, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x6_t", RvvFloat16mf4x6, RvvFloat16mf4x6Ty, 1, 16, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x7_t", RvvFloat16mf4x7, RvvFloat16mf4x7Ty, 1, 16, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4x8_t", RvvFloat16mf4x8, RvvFloat16mf4x8Ty, 1, 16, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x2_t", RvvFloat16mf2x2, RvvFloat16mf2x2Ty, 2, 16, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x3_t", RvvFloat16mf2x3, RvvFloat16mf2x3Ty, 2, 16, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x4_t", RvvFloat16mf2x4, RvvFloat16mf2x4Ty, 2, 16, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x5_t", RvvFloat16mf2x5, RvvFloat16mf2x5Ty, 2, 16, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x6_t", RvvFloat16mf2x6, RvvFloat16mf2x6Ty, 2, 16, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x7_t", RvvFloat16mf2x7, RvvFloat16mf2x7Ty, 2, 16, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2x8_t", RvvFloat16mf2x8, RvvFloat16mf2x8Ty, 2, 16, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x2_t", RvvFloat16m1x2, RvvFloat16m1x2Ty, 4, 16, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x3_t", RvvFloat16m1x3, RvvFloat16m1x3Ty, 4, 16, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x4_t", RvvFloat16m1x4, RvvFloat16m1x4Ty, 4, 16, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x5_t", RvvFloat16m1x5, RvvFloat16m1x5Ty, 4, 16, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x6_t", RvvFloat16m1x6, RvvFloat16m1x6Ty, 4, 16, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x7_t", RvvFloat16m1x7, RvvFloat16m1x7Ty, 4, 16, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1x8_t", RvvFloat16m1x8, RvvFloat16m1x8Ty, 4, 16, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2x2_t", RvvFloat16m2x2, RvvFloat16m2x2Ty, 8, 16, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2x3_t", RvvFloat16m2x3, RvvFloat16m2x3Ty, 8, 16, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2x4_t", RvvFloat16m2x4, RvvFloat16m2x4Ty, 8, 16, 4)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4x2_t", RvvFloat16m4x2, RvvFloat16m4x2Ty, 16, 16, 2)
+
+//===- Float32 tuple types --------------------------------------------------===//
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x2_t", RvvFloat32mf2x2, RvvFloat32mf2x2Ty, 1, 32, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x3_t", RvvFloat32mf2x3, RvvFloat32mf2x3Ty, 1, 32, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x4_t", RvvFloat32mf2x4, RvvFloat32mf2x4Ty, 1, 32, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x5_t", RvvFloat32mf2x5, RvvFloat32mf2x5Ty, 1, 32, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x6_t", RvvFloat32mf2x6, RvvFloat32mf2x6Ty, 1, 32, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x7_t", RvvFloat32mf2x7, RvvFloat32mf2x7Ty, 1, 32, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2x8_t", RvvFloat32mf2x8, RvvFloat32mf2x8Ty, 1, 32, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x2_t", RvvFloat32m1x2, RvvFloat32m1x2Ty, 2, 32, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x3_t", RvvFloat32m1x3, RvvFloat32m1x3Ty, 2, 32, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x4_t", RvvFloat32m1x4, RvvFloat32m1x4Ty, 2, 32, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x5_t", RvvFloat32m1x5, RvvFloat32m1x5Ty, 2, 32, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x6_t", RvvFloat32m1x6, RvvFloat32m1x6Ty, 2, 32, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x7_t", RvvFloat32m1x7, RvvFloat32m1x7Ty, 2, 32, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1x8_t", RvvFloat32m1x8, RvvFloat32m1x8Ty, 2, 32, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2x2_t", RvvFloat32m2x2, RvvFloat32m2x2Ty, 4, 32, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2x3_t", RvvFloat32m2x3, RvvFloat32m2x3Ty, 4, 32, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2x4_t", RvvFloat32m2x4, RvvFloat32m2x4Ty, 4, 32, 4)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m4x2_t", RvvFloat32m4x2, RvvFloat32m4x2Ty, 8, 32, 2)
+
+//===- Float64 tuple types -------------------------------------------------===//
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x2_t", RvvFloat64m1x2, RvvFloat64m1x2Ty, 1, 64, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x3_t", RvvFloat64m1x3, RvvFloat64m1x3Ty, 1, 64, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x4_t", RvvFloat64m1x4, RvvFloat64m1x4Ty, 1, 64, 4)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x5_t", RvvFloat64m1x5, RvvFloat64m1x5Ty, 1, 64, 5)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x6_t", RvvFloat64m1x6, RvvFloat64m1x6Ty, 1, 64, 6)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x7_t", RvvFloat64m1x7, RvvFloat64m1x7Ty, 1, 64, 7)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1x8_t", RvvFloat64m1x8, RvvFloat64m1x8Ty, 1, 64, 8)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x2_t", RvvFloat64m2x2, RvvFloat64m2x2Ty, 2, 64, 2)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x3_t", RvvFloat64m2x3, RvvFloat64m2x3Ty, 2, 64, 3)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t", RvvFloat64m2x4, RvvFloat64m2x4Ty, 2, 64, 4)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty, 4, 64, 2)
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
