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As the extension list continues to grow it probably makes sense
to use a binary search rather than linear search. Sorting the strings
will make this possible.
This also avoids any question about where to add new strings in
the tables.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D153170
Files:
clang/test/Driver/riscv-march-mcpu-mtune.c
llvm/lib/Support/RISCVISAInfo.cpp
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -44,119 +44,124 @@
};
static const RISCVSupportedExtension SupportedExtensions[] = {
- {"i", RISCVExtensionVersion{2, 1}},
- {"e", RISCVExtensionVersion{2, 0}},
- {"m", RISCVExtensionVersion{2, 0}},
{"a", RISCVExtensionVersion{2, 1}},
- {"f", RISCVExtensionVersion{2, 2}},
- {"d", RISCVExtensionVersion{2, 2}},
{"c", RISCVExtensionVersion{2, 0}},
-
+ {"d", RISCVExtensionVersion{2, 2}},
+ {"e", RISCVExtensionVersion{2, 0}},
+ {"f", RISCVExtensionVersion{2, 2}},
{"h", RISCVExtensionVersion{1, 0}},
+ {"i", RISCVExtensionVersion{2, 1}},
+ {"m", RISCVExtensionVersion{2, 0}},
- {"zihintpause", RISCVExtensionVersion{2, 0}},
+ {"svinval", RISCVExtensionVersion{1, 0}},
+ {"svnapot", RISCVExtensionVersion{1, 0}},
+ {"svpbmt", RISCVExtensionVersion{1, 0}},
- {"zfhmin", RISCVExtensionVersion{1, 0}},
- {"zfh", RISCVExtensionVersion{1, 0}},
+ {"v", RISCVExtensionVersion{1, 0}},
- {"zfinx", RISCVExtensionVersion{1, 0}},
- {"zdinx", RISCVExtensionVersion{1, 0}},
- {"zhinxmin", RISCVExtensionVersion{1, 0}},
- {"zhinx", RISCVExtensionVersion{1, 0}},
+ // vendor-defined ('X') extensions
+ {"xsfvcp", RISCVExtensionVersion{1, 0}},
+ {"xtheadba", RISCVExtensionVersion{1, 0}},
+ {"xtheadbb", RISCVExtensionVersion{1, 0}},
+ {"xtheadbs", RISCVExtensionVersion{1, 0}},
+ {"xtheadcmo", RISCVExtensionVersion{1, 0}},
+ {"xtheadcondmov", RISCVExtensionVersion{1, 0}},
+ {"xtheadfmemidx", RISCVExtensionVersion{1, 0}},
+ {"xtheadmac", RISCVExtensionVersion{1, 0}},
+ {"xtheadmemidx", RISCVExtensionVersion{1, 0}},
+ {"xtheadmempair", RISCVExtensionVersion{1, 0}},
+ {"xtheadsync", RISCVExtensionVersion{1, 0}},
+ {"xtheadvdot", RISCVExtensionVersion{1, 0}},
+ {"xventanacondops", RISCVExtensionVersion{1, 0}},
+
+ {"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
{"zbb", RISCVExtensionVersion{1, 0}},
{"zbc", RISCVExtensionVersion{1, 0}},
- {"zbs", RISCVExtensionVersion{1, 0}},
-
{"zbkb", RISCVExtensionVersion{1, 0}},
{"zbkc", RISCVExtensionVersion{1, 0}},
{"zbkx", RISCVExtensionVersion{1, 0}},
+ {"zbs", RISCVExtensionVersion{1, 0}},
+
+ {"zdinx", RISCVExtensionVersion{1, 0}},
+
+ {"zfh", RISCVExtensionVersion{1, 0}},
+ {"zfhmin", RISCVExtensionVersion{1, 0}},
+ {"zfinx", RISCVExtensionVersion{1, 0}},
+
+ {"zhinx", RISCVExtensionVersion{1, 0}},
+ {"zhinxmin", RISCVExtensionVersion{1, 0}},
+
+ {"zicbom", RISCVExtensionVersion{1, 0}},
+ {"zicbop", RISCVExtensionVersion{1, 0}},
+ {"zicboz", RISCVExtensionVersion{1, 0}},
+ {"zicntr", RISCVExtensionVersion{1, 0}},
+ {"zicsr", RISCVExtensionVersion{2, 0}},
+ {"zifencei", RISCVExtensionVersion{2, 0}},
+ {"zihintpause", RISCVExtensionVersion{2, 0}},
+ {"zihpm", RISCVExtensionVersion{1, 0}},
+
+ {"zk", RISCVExtensionVersion{1, 0}},
+ {"zkn", RISCVExtensionVersion{1, 0}},
{"zknd", RISCVExtensionVersion{1, 0}},
{"zkne", RISCVExtensionVersion{1, 0}},
{"zknh", RISCVExtensionVersion{1, 0}},
- {"zksed", RISCVExtensionVersion{1, 0}},
- {"zksh", RISCVExtensionVersion{1, 0}},
{"zkr", RISCVExtensionVersion{1, 0}},
- {"zkn", RISCVExtensionVersion{1, 0}},
{"zks", RISCVExtensionVersion{1, 0}},
+ {"zksed", RISCVExtensionVersion{1, 0}},
+ {"zksh", RISCVExtensionVersion{1, 0}},
{"zkt", RISCVExtensionVersion{1, 0}},
- {"zk", RISCVExtensionVersion{1, 0}},
{"zmmul", RISCVExtensionVersion{1, 0}},
- {"v", RISCVExtensionVersion{1, 0}},
- {"zvl32b", RISCVExtensionVersion{1, 0}},
- {"zvl64b", RISCVExtensionVersion{1, 0}},
- {"zvl128b", RISCVExtensionVersion{1, 0}},
- {"zvl256b", RISCVExtensionVersion{1, 0}},
- {"zvl512b", RISCVExtensionVersion{1, 0}},
+ {"zve32f", RISCVExtensionVersion{1, 0}},
+ {"zve32x", RISCVExtensionVersion{1, 0}},
+ {"zve64d", RISCVExtensionVersion{1, 0}},
+ {"zve64f", RISCVExtensionVersion{1, 0}},
+ {"zve64x", RISCVExtensionVersion{1, 0}},
{"zvl1024b", RISCVExtensionVersion{1, 0}},
- {"zvl2048b", RISCVExtensionVersion{1, 0}},
- {"zvl4096b", RISCVExtensionVersion{1, 0}},
- {"zvl8192b", RISCVExtensionVersion{1, 0}},
+ {"zvl128b", RISCVExtensionVersion{1, 0}},
{"zvl16384b", RISCVExtensionVersion{1, 0}},
+ {"zvl2048b", RISCVExtensionVersion{1, 0}},
+ {"zvl256b", RISCVExtensionVersion{1, 0}},
{"zvl32768b", RISCVExtensionVersion{1, 0}},
+ {"zvl32b", RISCVExtensionVersion{1, 0}},
+ {"zvl4096b", RISCVExtensionVersion{1, 0}},
+ {"zvl512b", RISCVExtensionVersion{1, 0}},
+ {"zvl64b", RISCVExtensionVersion{1, 0}},
{"zvl65536b", RISCVExtensionVersion{1, 0}},
- {"zve32x", RISCVExtensionVersion{1, 0}},
- {"zve32f", RISCVExtensionVersion{1, 0}},
- {"zve64x", RISCVExtensionVersion{1, 0}},
- {"zve64f", RISCVExtensionVersion{1, 0}},
- {"zve64d", RISCVExtensionVersion{1, 0}},
-
- {"zicbom", RISCVExtensionVersion{1, 0}},
- {"zicboz", RISCVExtensionVersion{1, 0}},
- {"zicbop", RISCVExtensionVersion{1, 0}},
- {"zicntr", RISCVExtensionVersion{1, 0}},
- {"zicsr", RISCVExtensionVersion{2, 0}},
- {"zifencei", RISCVExtensionVersion{2, 0}},
- {"zihpm", RISCVExtensionVersion{1, 0}},
-
- {"zawrs", RISCVExtensionVersion{1, 0}},
-
- {"svnapot", RISCVExtensionVersion{1, 0}},
- {"svpbmt", RISCVExtensionVersion{1, 0}},
- {"svinval", RISCVExtensionVersion{1, 0}},
-
- // vendor-defined ('X') extensions
- {"xsfvcp", RISCVExtensionVersion{1, 0}},
- {"xtheadba", RISCVExtensionVersion{1, 0}},
- {"xtheadbb", RISCVExtensionVersion{1, 0}},
- {"xtheadbs", RISCVExtensionVersion{1, 0}},
- {"xtheadcmo", RISCVExtensionVersion{1, 0}},
- {"xtheadcondmov", RISCVExtensionVersion{1, 0}},
- {"xtheadfmemidx", RISCVExtensionVersion{1, 0}},
- {"xtheadmac", RISCVExtensionVersion{1, 0}},
- {"xtheadmemidx", RISCVExtensionVersion{1, 0}},
- {"xtheadmempair", RISCVExtensionVersion{1, 0}},
- {"xtheadsync", RISCVExtensionVersion{1, 0}},
- {"xtheadvdot", RISCVExtensionVersion{1, 0}},
- {"xventanacondops", RISCVExtensionVersion{1, 0}},
+ {"zvl8192b", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"smaia", RISCVExtensionVersion{1, 0}},
{"ssaia", RISCVExtensionVersion{1, 0}},
- {"zihintntl", RISCVExtensionVersion{0, 2}},
-
{"zca", RISCVExtensionVersion{1, 0}},
{"zcb", RISCVExtensionVersion{1, 0}},
{"zcd", RISCVExtensionVersion{1, 0}},
{"zcf", RISCVExtensionVersion{1, 0}},
{"zcmp", RISCVExtensionVersion{1, 0}},
{"zcmt", RISCVExtensionVersion{1, 0}},
+
{"zfa", RISCVExtensionVersion{0, 2}},
{"zfbfmin", RISCVExtensionVersion{0, 6}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
+
+ {"zihintntl", RISCVExtensionVersion{0, 2}},
+
+ {"ztso", RISCVExtensionVersion{0, 1}},
+
+ {"zvbb", RISCVExtensionVersion{0, 9}},
+ {"zvbc", RISCVExtensionVersion{0, 9}},
+
{"zvfbfmin", RISCVExtensionVersion{0, 6}},
{"zvfbfwma", RISCVExtensionVersion{0, 6}},
{"zvfh", RISCVExtensionVersion{0, 1}},
- {"ztso", RISCVExtensionVersion{0, 1}},
// vector crypto
- {"zvbb", RISCVExtensionVersion{0, 9}},
- {"zvbc", RISCVExtensionVersion{0, 9}},
{"zvkg", RISCVExtensionVersion{0, 9}},
{"zvkn", RISCVExtensionVersion{0, 9}},
{"zvknc", RISCVExtensionVersion{0, 9}},
Index: clang/test/Driver/riscv-march-mcpu-mtune.c
===================================================================
--- clang/test/Driver/riscv-march-mcpu-mtune.c
+++ clang/test/Driver/riscv-march-mcpu-mtune.c
@@ -58,9 +58,9 @@
// RUN: | FileCheck -check-prefix=MCPU-E31-MARCH-RV32I %s
// MCPU-E31-MARCH-RV32I: "-target-cpu" "sifive-e31"
// MCPU-E31-MARCH-RV32I: "-target-feature" "+c"
-// MCPU-E31-MARCH-RV32I: "-target-feature" "-m"
// MCPU-E31-MARCH-RV32I: "-target-feature" "-a"
// MCPU-E31-MARCH-RV32I: "-target-feature" "-f"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-m"
// -mcpu, -march and -mtune are given, so pipeline model take from -mtune
// and arch ext. take from -march, -mcpu is unused.
@@ -68,7 +68,7 @@
// RUN: | FileCheck -check-prefix=MCPU-E31-MTUNE-E76-MARCH-RV32I %s
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-cpu" "sifive-e31"
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "+c"
-// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m"
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-a"
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-f"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m"
// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-tune-cpu" "sifive-e76"
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