fakepaper56 added reviewers: craig.topper, frasercrmck, rogfer01, reames, asb, luke. fakepaper56 marked an inline comment as done. fakepaper56 added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:56 +let Predicates = [HasStdExtZicfiss] in { +def SSLoadX1: RV_SSPop<0b00001, 0b00000, "ssload", "x1">; +def SSLoadX5: RV_SSPop<0b00101, 0b00000, "ssload", "x5">; ---------------- fakepaper56 wrote: > craig.topper wrote: > > Need to be able to parse with `ra` instead of x1 and `t0` instead of x5. > > > > I think you might need a new Operand type so the parse can parse it as a > > register. > > Need to be able to parse with ra instead of x1 and t0 instead of x5. > Actually, we can parse `ssload ra` in llvm/test/MC/RISCV/zicfiss-valid.s, but > the code indeed can not print `ssload ra`. I have tried to define `ssload` > and `sspopchk` separately, but it caused decode conflict. The problem is fixed in latest update. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152793/new/ https://reviews.llvm.org/D152793 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits