liaolucy updated this revision to Diff 553911.
liaolucy added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Address comments from Jim, thanks.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158824/new/
https://reviews.llvm.org/D158824
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/corev/XCVelw-invalid.s
llvm/test/MC/RISCV/corev/XCVelw-valid.s
llvm/test/MC/RISCV/corev/XCVmem-invalid.s
llvm/test/MC/RISCV/corev/XCVmem-valid.s
Index: llvm/test/MC/RISCV/corev/XCVmem-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/corev/XCVmem-valid.s
@@ -0,0 +1,247 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \
+# RUN: | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.lb t0, (t1), 0
+# CHECK-INSTR: cv.lb t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x02,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), 2047
+# CHECK-INSTR: cv.lb a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb t0, (t1), t2
+# CHECK-INSTR: cv.lb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb a0, (a1), a2
+# CHECK-INSTR: cv.lb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lb t0, t2(t1)
+# CHECK-INSTR: cv.lb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x08]
+# CHECK-NO-EXT: unexpected token
+
+cv.lb a0, a2(a1)
+# CHECK-INSTR: cv.lb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08]
+# CHECK-NO-EXT: unexpected token
+
+cv.lbu t0, (t1), 0
+# CHECK-INSTR: cv.lbu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x42,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), 2047
+# CHECK-INSTR: cv.lbu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, (t1), t2
+# CHECK-INSTR: cv.lbu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu a0, (a1), a2
+# CHECK-INSTR: cv.lbu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lbu t0, t2(t1)
+# CHECK-INSTR: cv.lbu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x18]
+# CHECK-NO-EXT: unexpected token
+
+cv.lbu a0, a2(a1)
+# CHECK-INSTR: cv.lbu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18]
+# CHECK-NO-EXT: unexpected token
+
+cv.lh t0, (t1), 0
+# CHECK-INSTR: cv.lh t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x12,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), 2047
+# CHECK-INSTR: cv.lh a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh t0, (t1), t2
+# CHECK-INSTR: cv.lh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh a0, (a1), a2
+# CHECK-INSTR: cv.lh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lh t0, t2(t1)
+# CHECK-INSTR: cv.lh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lh a0, a2(a1)
+# CHECK-INSTR: cv.lh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lhu t0, (t1), 0
+# CHECK-INSTR: cv.lhu t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x52,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), 2047
+# CHECK-INSTR: cv.lhu a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xd5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, (t1), t2
+# CHECK-INSTR: cv.lhu t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu a0, (a1), a2
+# CHECK-INSTR: cv.lhu a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x12]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lhu t0, t2(t1)
+# CHECK-INSTR: cv.lhu t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x1a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lhu a0, a2(a1)
+# CHECK-INSTR: cv.lhu a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x1a]
+# CHECK-NO-EXT: unexpected token
+
+cv.lw t0, (t1), 0
+# CHECK-INSTR: cv.lw t0, (t1), 0
+# CHECK-ENCODING: [0x8b,0x22,0x03,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), 2047
+# CHECK-INSTR: cv.lw a0, (a1), 2047
+# CHECK-ENCODING: [0x0b,0xa5,0xf5,0x7f]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw t0, (t1), t2
+# CHECK-INSTR: cv.lw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw a0, (a1), a2
+# CHECK-INSTR: cv.lw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x04]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.lw t0, t2(t1)
+# CHECK-INSTR: cv.lw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x32,0x73,0x0c]
+# CHECK-NO-EXT: unexpected token
+
+cv.lw a0, a2(a1)
+# CHECK-INSTR: cv.lw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0c]
+# CHECK-NO-EXT: unexpected token
+
+cv.sb t0, (t1), 0
+# CHECK-INSTR: cv.sb t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x00,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), 2047
+# CHECK-INSTR: cv.sb a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x8f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb t0, (t1), t2
+# CHECK-INSTR: cv.sb t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb a0, (a1), a2
+# CHECK-INSTR: cv.sb a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sb t0, t2(t1)
+# CHECK-INSTR: cv.sb t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x28]
+# CHECK-NO-EXT: unexpected token
+
+cv.sb a0, a2(a1)
+# CHECK-INSTR: cv.sb a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x28]
+# CHECK-NO-EXT: unexpected token
+
+cv.sh t0, (t1), 0
+# CHECK-INSTR: cv.sh t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x10,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), 2047
+# CHECK-INSTR: cv.sh a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0x9f,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh t0, (t1), t2
+# CHECK-INSTR: cv.sh t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh a0, (a1), a2
+# CHECK-INSTR: cv.sh a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x22]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sh t0, t2(t1)
+# CHECK-INSTR: cv.sh t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2a]
+# CHECK-NO-EXT: unexpected token
+
+cv.sh a0, a2(a1)
+# CHECK-INSTR: cv.sh a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2a]
+# CHECK-NO-EXT: unexpected token
+
+cv.sw t0, (t1), 0
+# CHECK-INSTR: cv.sw t0, (t1), 0
+# CHECK-ENCODING: [0x2b,0x20,0x53,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), 2047
+# CHECK-INSTR: cv.sw a0, (a1), 2047
+# CHECK-ENCODING: [0xab,0xaf,0xa5,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw t0, (t1), t2
+# CHECK-INSTR: cv.sw t0, (t1), t2
+# CHECK-ENCODING: [0xab,0x33,0x53,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw a0, (a1), a2
+# CHECK-INSTR: cv.sw a0, (a1), a2
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x24]
+# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}}
+
+cv.sw t0, t2(t1)
+# CHECK-INSTR: cv.sw t0, t2(t1)
+# CHECK-ENCODING: [0xab,0x33,0x53,0x2c]
+# CHECK-NO-EXT: unexpected token
+
+cv.sw a0, a2(a1)
+# CHECK-INSTR: cv.sw a0, a2(a1)
+# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2c]
+# CHECK-NO-EXT: unexpected token
Index: llvm/test/MC/RISCV/corev/XCVmem-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/corev/XCVmem-invalid.s
@@ -0,0 +1,223 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.lb t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lb t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t1), t2, t3
+
+cv.lbu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (0), t0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lbu t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lbu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lh t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu 0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lhu t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lhu 0, t0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lhu t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw 0, (0), t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, (t1), -2049
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.lw t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0, t1(0)
+# CHECK-ERROR: expected register
+
+cv.lw 0, (t0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.lw t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lw t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb 0, (t0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sb t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sh t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sh t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sh t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.sw t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw 0, (t1), 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0, 0(t1)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.sw t0, (0), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw 0, (t1), t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sw t0
+# CHECK-ERROR: too few operands for instruction
Index: llvm/test/MC/RISCV/corev/XCVelw-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/corev/XCVelw-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvelw -show-encoding %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvelw < %s \
+# RUN: | llvm-objdump --mattr=+xcvelw -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.elw a0, 1024(a0)
+# CHECK-INSTR: cv.elw a0, 1024(a0)
+# CHECK-ENCODING: [0x0b,0x35,0x05,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}}
+
+cv.elw a1, 1(a1)
+# CHECK-INSTR: cv.elw a1, 1(a1)
+# CHECK-ENCODING: [0x8b,0xb5,0x15,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}}
+
+cv.elw a2, -1024(a3)
+# CHECK-INSTR: cv.elw a2, -1024(a3)
+# CHECK-ENCODING: [0x0b,0xb6,0x06,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVelw' (CORE-V Event Load Word){{$}}
Index: llvm/test/MC/RISCV/corev/XCVelw-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/corev/XCVelw-invalid.s
@@ -0,0 +1,26 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvelw %s 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.elw t0, 0(0)
+# CHECK-ERROR: expected register
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x12, 2048(x6)
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+cv.elw x12, x1(2047)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw x12, x12(x6)
+# CHECK-ERROR: unexpected token
+
+cv.elw 0, 0(x6)
+# CHECK-ERROR: invalid operand for instruction
+
+cv.elw x0
+# CHECK-ERROR: too few operands for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -294,9 +294,15 @@
.attribute arch, "rv32i_xcvbitmanip"
# CHECK: attribute 5, "rv32i2p1_xcvbitmanip1p0"
+.attribute arch, "rv32i_xcvelw"
+# CHECK: attribute 5, "rv32i2p1_xcvelw1p0"
+
.attribute arch, "rv32i_xcvmac"
# CHECK: attribute 5, "rv32i2p1_xcvmac1p0"
+.attribute arch, "rv32i_xcvmem"
+# CHECK: attribute 5, "rv32i2p1_xcvmem1p0"
+
.attribute arch, "rv32i_xcvsimd"
# CHECK: attribute 5, "rv32i2p1_xcvsimd1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -43,7 +43,9 @@
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck --check-prefix=RV32XCVELW %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvmem %s -o - | FileCheck --check-prefix=RV32XCVMEM %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
@@ -223,7 +225,9 @@
; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
+; RV32XCVELW: .attribute 5, "rv32i2p1_xcvelw1p0"
; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
+; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -505,3 +505,134 @@
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
}
+
+class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
+ : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
+ opcodestr, "$rd, (${rs1}), ${imm12}"> {
+ let Constraints = "$rs1_wb = $rs1";
+ let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
+ opcodestr, "$rd, (${rs1}), ${rs2}"> {
+ let Constraints = "$rs1_wb = $rs1";
+ let DecoderNamespace = "XCVmem";
+}
+
+class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+ opcodestr, "$rd, ${rs2}(${rs1})"> {
+ let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+ mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
+ // Register-Immediate load with post-increment
+ def CV_LB_ri_inc : CVLoad_ri_inc<0b000, "cv.lb">;
+ def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
+ def CV_LH_ri_inc : CVLoad_ri_inc<0b001, "cv.lh">;
+ def CV_LHU_ri_inc : CVLoad_ri_inc<0b101, "cv.lhu">;
+ def CV_LW_ri_inc : CVLoad_ri_inc<0b010, "cv.lw">;
+
+ // Register-Register load with post-increment
+ def CV_LB_rr_inc : CVLoad_rr_inc<0b0000000, 0b011, "cv.lb">;
+ def CV_LBU_rr_inc : CVLoad_rr_inc<0b0001000, 0b011, "cv.lbu">;
+ def CV_LH_rr_inc : CVLoad_rr_inc<0b0000001, 0b011, "cv.lh">;
+ def CV_LHU_rr_inc : CVLoad_rr_inc<0b0001001, 0b011, "cv.lhu">;
+ def CV_LW_rr_inc : CVLoad_rr_inc<0b0000010, 0b011, "cv.lw">;
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+ mayLoad = 1, mayStore = 0 in {
+ // Register-Register load
+ def CV_LB_rr : CVLoad_rr<0b0000100, 0b011, "cv.lb">;
+ def CV_LBU_rr : CVLoad_rr<0b0001100, 0b011, "cv.lbu">;
+ def CV_LH_rr : CVLoad_rr<0b0000101, 0b011, "cv.lh">;
+ def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;
+ def CV_LW_rr : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
+}
+
+class CVStore_ri_inc<bits<3> funct3, string opcodestr>
+ : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
+ (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
+ opcodestr, "$rs2, (${rs1}), ${imm12}"> {
+ let Constraints = "$rs1_wb = $rs1";
+ let DecoderNamespace = "XCVmem";
+}
+
+class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rs3;
+ let Inst{6-0} = OPC_CUSTOM_1.Value;
+ let DecoderNamespace = "XCVmem";
+}
+
+class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rs3;
+ let Inst{6-0} = OPC_CUSTOM_1.Value;
+ let DecoderNamespace = "XCVmem";
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+ mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
+ // Register-Immediate store with post-increment
+ def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
+ def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;
+ def CV_SW_ri_inc : CVStore_ri_inc<0b010, "cv.sw">;
+
+ // Register-Register store with post-increment
+ def CV_SB_rr_inc : CVStore_rr_inc<0b011, 0b0010000,
+ (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sb", "$rs2, (${rs1}), ${rs3}">;
+ def CV_SH_rr_inc : CVStore_rr_inc<0b011, 0b0010001,
+ (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sh", "$rs2, (${rs1}), ${rs3}">;
+ def CV_SW_rr_inc : CVStore_rr_inc<0b011, 0b0010010,
+ (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sw", "$rs2, (${rs1}), ${rs3}">;
+}
+
+let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
+ mayLoad = 0, mayStore = 1 in {
+ // Register-Register store
+ def CV_SB_rr : CVStore_rr<0b011, 0b0010100,
+ (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sb", "$rs2, ${rs3}(${rs1})">;
+ def CV_SH_rr : CVStore_rr<0b011, 0b0010101,
+ (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sh", "$rs2, ${rs3}(${rs1})">;
+ def CV_SW_rr : CVStore_rr<0b011, 0b0010110,
+ (outs), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ "cv.sw", "$rs2, ${rs3}(${rs1})">;
+}
+
+let DecoderNamespace = "XCVelw" in
+class CVLoad_ri<bits<3> funct3, string opcodestr>
+ : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+ (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+
+let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0,
+ mayLoad = 1, mayStore = 0 in {
+ // Event load
+ def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
+}
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -813,6 +813,14 @@
AssemblerPredicate<(all_of FeatureVendorXSfcie),
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
+def FeatureVendorXCVelw
+ : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
+ "'XCVelw' (CORE-V Event Load Word)">;
+def HasVendorXCVelw
+ : Predicate<"Subtarget->hasVendorXCVelw()">,
+ AssemblerPredicate<(any_of FeatureVendorXCVelw),
+ "'XCVelw' (CORE-V Event Load Word)">;
+
def FeatureVendorXCVbitmanip
: SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
@@ -827,6 +835,14 @@
AssemblerPredicate<(all_of FeatureVendorXCVmac),
"'XCVmac' (CORE-V Multiply-Accumulate)">;
+def FeatureVendorXCVmem
+ : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true",
+ "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+def HasVendorXCVmem
+ : Predicate<"Subtarget->hasVendorXCVmem()">,
+ AssemblerPredicate<(any_of FeatureVendorXCVmem),
+ "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+
def FeatureVendorXCValu
: SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
"'XCValu' (CORE-V ALU Operations)">;
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -563,8 +563,12 @@
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
+ "CORE-V Event load custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
"CORE-V MAC custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
+ "CORE-V MEM custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
"CORE-V ALU custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2508,8 +2508,14 @@
return true;
// Attempt to parse token as a register.
- if (parseRegister(Operands, true).isSuccess())
+ if (parseRegister(Operands, true).isSuccess()) {
+ // Parse memory base register if present (CORE-V only)
+ if (getSTI().getFeatureBits()[RISCV::FeatureVendorXCVmem]) {
+ if (getLexer().is(AsmToken::LParen))
+ return !parseMemOpBaseReg(Operands).isSuccess();
+ }
return false;
+ }
// Attempt to parse token as an immediate
if (parseImmediate(Operands).isSuccess()) {
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -69,7 +69,9 @@
{"xcvalu", RISCVExtensionVersion{1, 0}},
{"xcvbi", RISCVExtensionVersion{1, 0}},
{"xcvbitmanip", RISCVExtensionVersion{1, 0}},
+ {"xcvelw", RISCVExtensionVersion{1, 0}},
{"xcvmac", RISCVExtensionVersion{1, 0}},
+ {"xcvmem", RISCVExtensionVersion{1, 0}},
{"xcvsimd", RISCVExtensionVersion{1, 0}},
{"xsfcie", RISCVExtensionVersion{1, 0}},
{"xsfvcp", RISCVExtensionVersion{1, 0}},
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -269,9 +269,15 @@
``XCVbitmanip``
LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification.
+``XCVelw``
+ LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
``XCVmac``
LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
+``XCVmem``
+ LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
``XCValu``
LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -29,7 +29,9 @@
// CHECK-NOT: __riscv_xcvalu {{.*$}}
// CHECK-NOT: __riscv_xcvbi {{.*$}}
// CHECK-NOT: __riscv_xcvbitmanip {{.*$}}
+// CHECK-NOT: __riscv_xcvelw {{.*$}}
// CHECK-NOT: __riscv_xcvmac {{.*$}}
+// CHECK-NOT: __riscv_xcvmem {{.*$}}
// CHECK-NOT: __riscv_xcvsimd {{.*$}}
// CHECK-NOT: __riscv_xsfcie {{.*$}}
// CHECK-NOT: __riscv_xsfvcp {{.*$}}
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