[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:52
 // Same as CSR_Interrupt, but including all 64-bit FP registers.
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
                                              (sequence "F%u_D", 0, 31))>;
----------------
Should we add CSRs for interrupt functions? And Should we save `vtype`, 
`vstart`, `vxrm`, `vxsat`, etc. registers?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154576/new/

https://reviews.llvm.org/D154576

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