================ @@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", + "'Zcmop' (Compressed May-Be-Operations)", + [FeatureStdExtZca]>; ---------------- kito-cheng wrote:
My understanding for those terminology on RISC-V ISA spec is: imply == depend == require See comment from Krste and Andrew in this issue: https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867 https://github.com/llvm/llvm-project/pull/76395 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits