https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/78489
>From a69c187716153c90f50b2859212a0e5af9102fd1 Mon Sep 17 00:00:00 2001 From: Min Hsu <min....@sifive.com> Date: Wed, 17 Jan 2024 10:28:14 -0800 Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0 Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data. --- llvm/lib/Support/RISCVISAInfo.cpp | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 + 5 files changed, 16 insertions(+) diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index d991878a5f1eca..bb62ea119506f5 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"m", {2, 0}}, {"smaia", {1, 0}}, + {"smepmp", {1, 0}}, {"ssaia", {1, 0}}, {"svinval", {1, 0}}, {"svnapot", {1, 0}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index fa334c69ddc982..5e8e09af457112 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -717,6 +717,13 @@ def FeatureStdExtSmaia "'Smaia' (Advanced Interrupt Architecture Machine " "Level)", []>; +def FeatureStdExtSmepmp + : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", + "'Smepmp' (Smepmp prevents privileged processes from " + "executing or accessing unprivileged programs and" + "data.)", + []>; + def FeatureStdExtSsaia : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", "'Ssaia' (Advanced Interrupt Architecture Supervisor " diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 60ef404ac345d1..ed2d88a45bd7fc 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -88,6 +88,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s +; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s @@ -182,6 +183,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s +; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s @@ -278,6 +280,7 @@ ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1" ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2" ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" +; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" @@ -371,6 +374,7 @@ ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1" ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" +; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 0e508bb80f6b94..0eb8d493bcd36b 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -270,6 +270,9 @@ .attribute arch, "rv32i_smaia1p0" # CHECK: attribute 5, "rv32i2p1_smaia1p0" +.attribute arch, "rv32i_smepmp1p0" +# CHECK: attribute 5, "rv32i2p1_smepmp1p0" + .attribute arch, "rv32i_ssaia1p0" # CHECK: attribute 5, "rv32i2p1_ssaia1p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index c8e77cdccf4e8a..e916bea3e2985c 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -753,6 +753,7 @@ R"(All available -march extensions for RISC-V zhinx 1.0 zhinxmin 1.0 smaia 1.0 + smepmp 1.0 ssaia 1.0 svinval 1.0 svnapot 1.0 >From 0dbbab9da7f3f4d7356c0e4eabc3676031b472dd Mon Sep 17 00:00:00 2001 From: Min Hsu <min....@sifive.com> Date: Wed, 17 Jan 2024 14:18:37 -0800 Subject: [PATCH 2/3] fixup! [RISCV] Add support for Smepmp 1.0 --- clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++ llvm/docs/RISCVUsage.rst | 1 + llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 12 +++++------- llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++---- llvm/test/MC/RISCV/attribute-arch.s | 6 +++--- 6 files changed, 23 insertions(+), 14 deletions(-) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index fd0970bd87fd14..407429566c1069 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -116,6 +116,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_smepmp {{.*$}} // CHECK-NOT: __riscv_zacas {{.*$}} // CHECK-NOT: __riscv_zfa {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} @@ -1047,6 +1048,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s // CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64ismepmp1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s +// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zacas1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 40fbaaa24e839a..3c78483a5e834b 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -92,6 +92,7 @@ on support follow. ``H`` Assembly Support ``M`` Supported ``Smaia`` Supported + ``Smepmp`` Supported ``Ssaia`` Supported ``Svinval`` Assembly Support ``Svnapot`` Assembly Support diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index e02f68f07d93bb..af32374d8a1d94 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -157,6 +157,7 @@ Changes to the RISC-V Backend * ``-mcpu=sifive-p450`` was added. * CodeGen of RV32E/RV64E was supported experimentally. * CodeGen of ilp32e/lp64e was supported experimentally. +* The Smepmp 1.0 extension is now supported. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 5e8e09af457112..d33ec5ac2ad442 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -717,18 +717,16 @@ def FeatureStdExtSmaia "'Smaia' (Advanced Interrupt Architecture Machine " "Level)", []>; -def FeatureStdExtSmepmp - : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", - "'Smepmp' (Smepmp prevents privileged processes from " - "executing or accessing unprivileged programs and" - "data.)", - []>; - def FeatureStdExtSsaia : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", "'Ssaia' (Advanced Interrupt Architecture Supervisor " "Level)", []>; +def FeatureStdExtSmepmp + : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", + "'Smepmp' (PMP Enhancements for memory access and " + "execution prevention on Machine mode)", []>; + def HasHalfFPLoadStoreMove : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index ed2d88a45bd7fc..4de06ad444ac55 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -88,8 +88,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s -; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s +; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s @@ -183,8 +183,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s -; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s +; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s @@ -280,8 +280,8 @@ ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1" ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2" ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" -; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" +; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" @@ -374,8 +374,8 @@ ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1" ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" -; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" +; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 0eb8d493bcd36b..c8882d79ae2bc3 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -270,12 +270,12 @@ .attribute arch, "rv32i_smaia1p0" # CHECK: attribute 5, "rv32i2p1_smaia1p0" -.attribute arch, "rv32i_smepmp1p0" -# CHECK: attribute 5, "rv32i2p1_smepmp1p0" - .attribute arch, "rv32i_ssaia1p0" # CHECK: attribute 5, "rv32i2p1_ssaia1p0" +.attribute arch, "rv32i_smepmp1p0" +# CHECK: attribute 5, "rv32i2p1_smepmp1p0" + .attribute arch, "rv32i_zfbfmin1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" >From a05871bbc2bcbfc235ec632cc6776e25da706641 Mon Sep 17 00:00:00 2001 From: Min Hsu <min....@sifive.com> Date: Thu, 18 Jan 2024 11:24:24 -0800 Subject: [PATCH 3/3] Shorten the description in RISCVFeatures.td --- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d33ec5ac2ad442..5fab46696cfd24 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -724,8 +724,7 @@ def FeatureStdExtSsaia def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", - "'Smepmp' (PMP Enhancements for memory access and " - "execution prevention on Machine mode)", []>; + "'Smepmp' (Enhanced Physical Memory Protection)", []>; def HasHalfFPLoadStoreMove : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits