https://github.com/sdesmalen-arm commented:
Generalising this code makes sense, 16 should never have been hardcoded here. Is it possible to add a test for the case where the predicate type is not `<vscale x 16 x i1>`? > Though I do wonder if we have the bitcast on the wrong side. Maybe we should > be casting the fixed type to an i1 fixed vector? That would better handle > cases where the mininum elements isn't a multiple of 8, but > vscale*min_elements is. I'm not sure if there are any fundamental reasons not to do this, but at least for AArch64 `16 x i1` is not a legal type which leads to some inefficient legalisation code. I can see however that the IR is missing some folds, so perhaps with those folds added making this change is fine. https://github.com/llvm/llvm-project/pull/76548 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
