[clang] [llvm] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP (PR #88251)

[via cfe-commits]

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@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
   def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]",  "44dd",   "csil",     
MergeNone, "aarch64_sve_sclamp_single_x4",  [IsStreaming], []>;
   def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]",  "44dd",   "UcUsUiUl", 
MergeNone, "aarch64_sve_uclamp_single_x4",  [IsStreaming], []>;
   def SVFCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]",  "44dd",   "hfd",      
MergeNone, "aarch64_sve_fclamp_single_x4",  [IsStreaming], []>;
+
+  let TargetGuard = "b16b16"in {
----------------
Lukacma wrote:

Fixed. Also added SEMA test for this

https://github.com/llvm/llvm-project/pull/88251
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