nemanjai added a comment.

Thank you for fixing these issues. I certainly see how the shifts really need 
to get the signedness right because the right shifts need to fill with the sign 
bit (so that vector bool will still have all 0 or all 1 bits). However, I don't 
really follow why the comparisons need to be signed. Could you just elaborate a 
bit on that?
Other than satisfying my curiosity on that, this LGTM.


https://reviews.llvm.org/D27251



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