https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/90143
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Neoverse-N3: https://developer.arm.com/documentation/107997/latest/ Technical Reference Manual for Neoverse-V3: https://developer.arm.com/documentation/107734/latest/ Technical Reference Manual for Neoverse-V3AE: https://developer.arm.com/documentation/101595/latest/ >From 5ced9f33871ea66647e04f62c637b92259805c2e Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <jonathan.thack...@arm.com> Date: Tue, 2 Apr 2024 22:08:50 +0100 Subject: [PATCH] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Neoverse-N3: https://developer.arm.com/documentation/107997/latest/ Technical Reference Manual for Neoverse-V3: https://developer.arm.com/documentation/107734/latest/ Technical Reference Manual for Neoverse-V3AE: https://developer.arm.com/documentation/101595/latest/ --- clang/docs/ReleaseNotes.rst | 3 + clang/test/Driver/aarch64-mcpu.c | 6 ++ clang/test/Misc/target-invalid-cpu-note.c | 4 +- llvm/docs/ReleaseNotes.rst | 3 +- .../llvm/TargetParser/AArch64TargetParser.h | 21 +++++++ llvm/lib/Target/AArch64/AArch64Processors.td | 46 +++++++++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 + llvm/lib/TargetParser/Host.cpp | 3 + .../TargetParser/TargetParserTest.cpp | 58 ++++++++++++++++++- 9 files changed, 142 insertions(+), 4 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 00c684e773a2e0..4b768db003b273 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -640,6 +640,9 @@ Arm and AArch64 Support * Arm Cortex-A78AE (cortex-a78ae). * Arm Cortex-A520AE (cortex-a520ae). * Arm Cortex-A720AE (cortex-a720ae). + * Arm Neoverse-N3 (neoverse-n3). + * Arm Neoverse-V3 (neoverse-v3). + * Arm Neoverse-V3AE (neoverse-v3ae). Android Support ^^^^^^^^^^^^^^^ diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c index 77ba43122b2453..ad4a5f9ac6fb80 100644 --- a/clang/test/Driver/aarch64-mcpu.c +++ b/clang/test/Driver/aarch64-mcpu.c @@ -64,10 +64,16 @@ // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1" // RUN: %clang --target=aarch64 -mcpu=neoverse-v2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V2 %s // NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2" +// RUN: %clang --target=aarch64 -mcpu=neoverse-v3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3 %s +// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3" +// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3AE %s +// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3ae" // RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N1 %s // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n1" // RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2" +// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N3 %s +// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n3" // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-512TVB %s // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-512tvb" // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520 %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 9c91c4157cd6a0..21d80b7134508f 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 6ef6ec20da671d..a83b8bb79a1c99 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -69,7 +69,8 @@ Changes to Interprocedural Optimizations Changes to the AArch64 Backend ------------------------------ -* Added support for Cortex-A78AE, Cortex-A520AE and Cortex-A720AE CPUs. +* Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE, + Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs. Changes to the AMDGPU Backend ----------------------------- diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 805b963a7a13c7..10a926b969e5d6 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -677,6 +677,13 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM})}, + {"neoverse-n3", ARMV9_2A, + AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})}, {"neoverse-512tvb", ARMV8_4A, AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, @@ -697,6 +704,20 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_RAND, AArch64::AEK_DOTPROD, AArch64::AEK_PROFILE, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE})}, + {"neoverse-v3", ARMV9_2A, + AArch64::ExtensionBitset( + {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, + AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML})}, + {"neoverse-v3ae", ARMV9_2A, + (AArch64::ExtensionBitset( + {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, + AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML}))}, {"cyclone", ARMV8A, AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index c50a8200dd898d..8ca4357ca7bf9d 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -447,6 +447,16 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2 FeatureEnableSelectOptimize, FeaturePredictableSelectIsExpensive]>; +def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily", "NeoverseN3", + "Neoverse N3 ARM processors", [ + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureCmpBccFusion, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", "Neoverse 512-TVB ARM processors", [ FeatureFuseAES, @@ -476,6 +486,24 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2 FeatureEnableSelectOptimize, FeaturePredictableSelectIsExpensive]>; +def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3", + "Neoverse V3 ARM processors", [ + FeatureFuseAES, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + +def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "NeoverseV3", + "Neoverse V3AE ARM processors", [ + FeatureFuseAES, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", "Qualcomm Saphira processors", [ FeaturePostRAScheduler, @@ -715,6 +743,10 @@ def ProcessorFeatures { FeatureMatMulInt8, FeatureMTE, FeatureSVE2, FeatureSVE2BitPerm, FeatureTRBE, FeaturePerfMon]; + list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureMTE, FeaturePerfMon, + FeatureRandGen, FeatureSPE, FeatureSPE_EEF, + FeatureSVE2BitPerm]; list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, @@ -729,6 +761,14 @@ def ProcessorFeatures { FeaturePerfMon, FeatureETE, FeatureMatMulInt8, FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMTE, FeatureRandGen]; + list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureLS64, FeatureMTE, + FeaturePerfMon, FeatureRandGen, FeatureSPE, + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; + list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureLS64, FeatureMTE, + FeaturePerfMon, FeatureRandGen, FeatureSPE, + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon]; list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, @@ -831,12 +871,18 @@ def : ProcessorModel<"neoverse-n1", NeoverseN1Model, ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; def : ProcessorModel<"neoverse-n2", NeoverseN2Model, ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; +def : ProcessorModel<"neoverse-n3", NeoverseN2Model, + ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>; def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; def : ProcessorModel<"neoverse-v1", NeoverseV1Model, ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; def : ProcessorModel<"neoverse-v2", NeoverseV2Model, ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; +def : ProcessorModel<"neoverse-v3", NeoverseV2Model, + ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; +def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, + ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index ef09a3cde49545..7d34dd1c776878 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -234,7 +234,9 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { MaxBytesForLoopAlignment = 16; break; case NeoverseN2: + case NeoverseN3: case NeoverseV2: + case NeoverseV3: PrefFunctionAlignment = Align(16); PrefLoopAlignment = Align(32); MaxBytesForLoopAlignment = 16; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index d2c9bae97364e9..0a93b06f40c248 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -245,8 +245,11 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd4a", "neoverse-e1") .Case("0xd0c", "neoverse-n1") .Case("0xd49", "neoverse-n2") + .Case("0xd8e", "neoverse-n3") .Case("0xd40", "neoverse-v1") .Case("0xd4f", "neoverse-v2") + .Case("0xd84", "neoverse-v3") + .Case("0xd83", "neoverse-v3ae") .Default("generic"); } diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 2c72a7229b5274..75e235008b4f25 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1345,6 +1345,44 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), "9-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "neoverse-v3", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_LS64, AArch64::AEK_BRBE, + AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, + AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, + AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA}), + "9.2-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "neoverse-v3ae", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_LS64, AArch64::AEK_BRBE, + AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, + AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, + AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA}), + "9.2-A"), ARMCPUTestParams<AArch64::ExtensionBitset>( "cortex-r82", "armv8-r", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( @@ -1636,6 +1674,24 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FP16FML}), "9-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "neoverse-n3", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, + AArch64::AEK_JSCVT}), + "9.2-A"), ARMCPUTestParams<AArch64::ExtensionBitset>( "ampere1", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( @@ -1750,7 +1806,7 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 72; +static constexpr unsigned NumAArch64CPUArchs = 75; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
