tmatheson-arm wrote: Summary of the PR after the recent changes:
- `CPUInfo` in `TargetParser` is now generated from `AArch64Processors.td` - The printed order of CPUs has changed, due to definition order. - `+perfmon` now appears in `target-features` for some CPUs. This is because `FeaturePerfMon` was in the list of `SubtargetFeature`s for the CPU but not in the `TargetParser` `CPUInfo`, which is now generated from the list of features. This is reflected in `TargetParserTest.cpp`. - The same applies to `+sb` and `+ssbs` in the case of `apple-m1`, `+complxnum` for `a64fx`, `+wfxt` for `ampere1b`. - References to `FeatureCrypto` in CPU feature lists were replaced by `FeatureSHA2` + `FeatureAES`. This prevents `+crypto` being output by `TargetParser`. - Made "generic" a real CPU in AArch64Processors.td. This removes some special treatment in code, and makes "generic" appear in the list of CPUs. It also means some `"target-features"="+fp-armv8,+neon"` appear for the generic CPU. `NumAArch64CPUArchs` increases. - Some CPUs specified AEK_NONE as an extension. This looks like a mistake, removed. The `AArch64Processor` class still takes a top-level reference to an architecture. https://github.com/llvm/llvm-project/pull/92145 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
