[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Matt Arsenault via cfe-commits]

================
@@ -5456,43 +5444,32 @@ bool 
AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
   if ((Size % 32) == 0) {
     SmallVector<Register, 2> PartialRes;
     unsigned NumParts = Size / 32;
-    auto IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
+    bool IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
----------------
arsenm wrote:

Better to track this as the LLT to use for the pieces, rather than making it 
this conditional thing. This will simplify improved pointer handling in the 
future 

https://github.com/llvm/llvm-project/pull/89217
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits