github-actions[bot] wrote: <!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning: <details> <summary> You can test this locally with the following command: </summary> ``````````bash git-clang-format --diff 781b13538e55a42b2d02bb4d21779f15ff8a640c 6e68c960bde622eb244f726d97982219b08a68bf -- clang/include/clang/Sema/SemaAMDGPU.h clang/include/clang/Sema/SemaARM.h clang/include/clang/Sema/SemaBPF.h clang/include/clang/Sema/SemaHexagon.h clang/include/clang/Sema/SemaLoongArch.h clang/include/clang/Sema/SemaMIPS.h clang/include/clang/Sema/SemaNVPTX.h clang/include/clang/Sema/SemaPPC.h clang/include/clang/Sema/SemaSystemZ.h clang/include/clang/Sema/SemaWasm.h clang/lib/Sema/SemaAMDGPU.cpp clang/lib/Sema/SemaARM.cpp clang/lib/Sema/SemaBPF.cpp clang/lib/Sema/SemaHexagon.cpp clang/lib/Sema/SemaLoongArch.cpp clang/lib/Sema/SemaMIPS.cpp clang/lib/Sema/SemaNVPTX.cpp clang/lib/Sema/SemaPPC.cpp clang/lib/Sema/SemaSystemZ.cpp clang/lib/Sema/SemaWasm.cpp clang/include/clang/Sema/Sema.h clang/lib/Parse/ParseOpenMP.cpp clang/lib/Sema/Sema.cpp clang/lib/Sema/SemaChecking.cpp clang/lib/Sema/SemaDecl.cpp clang/lib/Sema/SemaDeclAttr.cpp clang/lib/Sema/SemaExprCXX.cpp clang/lib/Sema/SemaTemplateInstantiateDecl.cpp clang/utils/TableGen/MveEmitter.cpp `````````` </details> <details> <summary> View the diff from clang-format here. </summary> ``````````diff diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index c1280190ff..f6e4a28d44 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -1082,11 +1082,18 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, // range check them here. unsigned i = 0, l = 0, u = 0; switch (BuiltinID) { - default: return false; + default: + return false; case AArch64::BI__builtin_arm_dmb: case AArch64::BI__builtin_arm_dsb: - case AArch64::BI__builtin_arm_isb: l = 0; u = 15; break; - case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break; + case AArch64::BI__builtin_arm_isb: + l = 0; + u = 15; + break; + case AArch64::BI__builtin_arm_tcancel: + l = 0; + u = 65535; + break; } return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u + l); diff --git a/clang/lib/Sema/SemaHexagon.cpp b/clang/lib/Sema/SemaHexagon.cpp index 5c921c0bc9..25331fc3b3 100644 --- a/clang/lib/Sema/SemaHexagon.cpp +++ b/clang/lib/Sema/SemaHexagon.cpp @@ -35,214 +35,200 @@ bool SemaHexagon::CheckHexagonBuiltinArgument(unsigned BuiltinID, }; static BuiltinInfo Infos[] = { - { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} }, - { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} }, - { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} }, - { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} }, - { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} }, - { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} }, - { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} }, - { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} }, - { Hexagon::BI__builtin_circ_sth, {{ 3, true, 4, 1 }} }, - { Hexagon::BI__builtin_circ_sthhi, {{ 3, true, 4, 1 }} }, - { Hexagon::BI__builtin_circ_stb, {{ 3, true, 4, 0 }} }, + {Hexagon::BI__builtin_circ_ldd, {{3, true, 4, 3}}}, + {Hexagon::BI__builtin_circ_ldw, {{3, true, 4, 2}}}, + {Hexagon::BI__builtin_circ_ldh, {{3, true, 4, 1}}}, + {Hexagon::BI__builtin_circ_lduh, {{3, true, 4, 1}}}, + {Hexagon::BI__builtin_circ_ldb, {{3, true, 4, 0}}}, + {Hexagon::BI__builtin_circ_ldub, {{3, true, 4, 0}}}, + {Hexagon::BI__builtin_circ_std, {{3, true, 4, 3}}}, + {Hexagon::BI__builtin_circ_stw, {{3, true, 4, 2}}}, + {Hexagon::BI__builtin_circ_sth, {{3, true, 4, 1}}}, + {Hexagon::BI__builtin_circ_sthhi, {{3, true, 4, 1}}}, + {Hexagon::BI__builtin_circ_stb, {{3, true, 4, 0}}}, - { Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{ 1, true, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{ 1, true, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{ 1, true, 4, 1 }} }, - { Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{ 1, true, 4, 1 }} }, - { Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{ 1, true, 4, 2 }} }, - { Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{ 1, true, 4, 3 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{ 1, true, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{ 1, true, 4, 1 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{ 1, true, 4, 1 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{ 1, true, 4, 2 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{ 1, true, 4, 3 }} }, + {Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{1, true, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{1, true, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{1, true, 4, 1}}}, + {Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{1, true, 4, 1}}}, + {Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{1, true, 4, 2}}}, + {Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{1, true, 4, 3}}}, + {Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{1, true, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{1, true, 4, 1}}}, + {Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{1, true, 4, 1}}}, + {Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{1, true, 4, 2}}}, + {Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{1, true, 4, 3}}}, - { Hexagon::BI__builtin_HEXAGON_A2_combineii, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{ 1, false, 16, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A2_tfril, {{ 1, false, 16, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{ 0, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{ 1, false, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{ 1, false, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{ 1, false, 7, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{ 1, false, 7, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{ 1, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{ 1, false, 7, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_C2_muxii, {{ 2, true, 8, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{ 0, false, 10, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{ 0, false, 10, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{ 0, false, 10, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{ 0, false, 10, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{ 1, false, 6, 2 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax, - {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax, - {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_extractu, {{ 1, false, 5, 0 }, - { 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_extractup, {{ 1, false, 6, 0 }, - { 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_insert, {{ 2, false, 5, 0 }, - { 3, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_insertp, {{ 2, false, 6, 0 }, - { 3, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax, - {{ 2, false, 4, 0 }, - { 3, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax, - {{ 2, false, 4, 0 }, - { 3, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax, - {{ 2, false, 4, 0 }, - { 3, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax, - {{ 2, false, 4, 0 }, - { 3, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_valignib, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{ 1, true , 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{ 1, true, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_extract, {{ 1, false, 5, 0 }, - { 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_extractp, {{ 1, false, 6, 0 }, - { 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_lsli, {{ 0, true, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{ 3, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{ 2, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax, - {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax, - {{ 1, false, 4, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{ 1, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{ 2, false, 6, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{ 1, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{ 2, false, 5, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{ 3, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B, - {{ 3, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{ 3, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B, - {{ 3, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{ 2, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{ 3, false, 1, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B, - {{ 3, false, 1, 0 }} }, + {Hexagon::BI__builtin_HEXAGON_A2_combineii, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{1, false, 16, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A2_tfril, {{1, false, 16, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{0, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{1, false, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{1, false, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{1, false, 7, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{1, false, 7, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{1, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{1, false, 7, 0}}}, + {Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_C2_muxii, {{2, true, 8, 0}}}, + {Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{0, false, 10, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{0, false, 10, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{0, false, 10, 0}}}, + {Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{0, false, 10, 0}}}, + {Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{1, false, 6, 2}}}, + {Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax, + {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax, + {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_extractu, + {{1, false, 5, 0}, {2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_extractup, + {{1, false, 6, 0}, {2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_insert, + {{2, false, 5, 0}, {3, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_insertp, + {{2, false, 6, 0}, {3, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax, + {{2, false, 4, 0}, {3, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax, + {{2, false, 4, 0}, {3, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax, + {{2, false, 4, 0}, {3, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax, + {{2, false, 4, 0}, {3, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_valignib, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{1, true, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{1, true, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_extract, + {{1, false, 5, 0}, {2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_extractp, + {{1, false, 6, 0}, {2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_lsli, {{0, true, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{3, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{2, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax, + {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax, {{1, false, 4, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{1, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{2, false, 6, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{1, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{2, false, 5, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{3, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B, {{3, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{3, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B, {{3, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{2, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{3, false, 1, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B, {{3, false, 1, 0}}}, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{ 2, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B, - {{ 2, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx, - {{ 3, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B, - {{ 3, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{ 2, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B, - {{ 2, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx, - {{ 3, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B, - {{ 3, false, 2, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{ 3, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B, - {{ 3, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{ 2, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{ 3, false, 3, 0 }} }, - { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B, - {{ 3, false, 3, 0 }} }, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{2, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B, {{2, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx, {{3, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B, + {{3, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{2, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B, {{2, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx, {{3, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B, + {{3, false, 2, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{3, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B, {{3, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{2, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{3, false, 3, 0}}}, + {Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B, {{3, false, 3, 0}}}, }; // Use a dynamically initialized static to sort the table exactly once on diff --git a/clang/lib/Sema/SemaMIPS.cpp b/clang/lib/Sema/SemaMIPS.cpp index df5328fbf6..fc4768ec3f 100644 --- a/clang/lib/Sema/SemaMIPS.cpp +++ b/clang/lib/Sema/SemaMIPS.cpp @@ -63,14 +63,43 @@ bool SemaMIPS::CheckMipsBuiltinCpu(const TargetInfo &TI, unsigned BuiltinID, bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { unsigned i = 0, l = 0, u = 0, m = 0; switch (BuiltinID) { - default: return false; - case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break; - case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63; break; - case Mips::BI__builtin_mips_append: i = 2; l = 0; u = 31; break; - case Mips::BI__builtin_mips_balign: i = 2; l = 0; u = 3; break; - case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31; break; - case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31; break; - case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31; break; + default: + return false; + case Mips::BI__builtin_mips_wrdsp: + i = 1; + l = 0; + u = 63; + break; + case Mips::BI__builtin_mips_rddsp: + i = 0; + l = 0; + u = 63; + break; + case Mips::BI__builtin_mips_append: + i = 2; + l = 0; + u = 31; + break; + case Mips::BI__builtin_mips_balign: + i = 2; + l = 0; + u = 3; + break; + case Mips::BI__builtin_mips_precr_sra_ph_w: + i = 2; + l = 0; + u = 31; + break; + case Mips::BI__builtin_mips_precr_sra_r_ph_w: + i = 2; + l = 0; + u = 31; + break; + case Mips::BI__builtin_mips_prepend: + i = 2; + l = 0; + u = 31; + break; // MSA intrinsics. Instructions (which the intrinsics maps to) which use the // df/m field. // These intrinsics take an unsigned 3 bit immediate. @@ -83,9 +112,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_srai_b: case Mips::BI__builtin_msa_srari_b: case Mips::BI__builtin_msa_srli_b: - case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7; break; + case Mips::BI__builtin_msa_srlri_b: + i = 1; + l = 0; + u = 7; + break; case Mips::BI__builtin_msa_binsli_b: - case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7; break; + case Mips::BI__builtin_msa_binsri_b: + i = 2; + l = 0; + u = 7; + break; // These intrinsics take an unsigned 4 bit immediate. case Mips::BI__builtin_msa_bclri_h: case Mips::BI__builtin_msa_bnegi_h: @@ -96,14 +133,26 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_srai_h: case Mips::BI__builtin_msa_srari_h: case Mips::BI__builtin_msa_srli_h: - case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15; break; + case Mips::BI__builtin_msa_srlri_h: + i = 1; + l = 0; + u = 15; + break; case Mips::BI__builtin_msa_binsli_h: - case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15; break; + case Mips::BI__builtin_msa_binsri_h: + i = 2; + l = 0; + u = 15; + break; // These intrinsics take an unsigned 5 bit immediate. // The first block of intrinsics actually have an unsigned 5 bit field, // not a df/n field. case Mips::BI__builtin_msa_cfcmsa: - case Mips::BI__builtin_msa_ctcmsa: i = 0; l = 0; u = 31; break; + case Mips::BI__builtin_msa_ctcmsa: + i = 0; + l = 0; + u = 31; + break; case Mips::BI__builtin_msa_clei_u_b: case Mips::BI__builtin_msa_clei_u_h: case Mips::BI__builtin_msa_clei_u_w: @@ -137,9 +186,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_subvi_b: case Mips::BI__builtin_msa_subvi_h: case Mips::BI__builtin_msa_subvi_w: - case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31; break; + case Mips::BI__builtin_msa_subvi_d: + i = 1; + l = 0; + u = 31; + break; case Mips::BI__builtin_msa_binsli_w: - case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31; break; + case Mips::BI__builtin_msa_binsri_w: + i = 2; + l = 0; + u = 31; + break; // These intrinsics take an unsigned 6 bit immediate. case Mips::BI__builtin_msa_bclri_d: case Mips::BI__builtin_msa_bnegi_d: @@ -150,9 +207,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_srai_d: case Mips::BI__builtin_msa_srari_d: case Mips::BI__builtin_msa_srli_d: - case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63; break; + case Mips::BI__builtin_msa_srlri_d: + i = 1; + l = 0; + u = 63; + break; case Mips::BI__builtin_msa_binsli_d: - case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63; break; + case Mips::BI__builtin_msa_binsri_d: + i = 2; + l = 0; + u = 63; + break; // These intrinsics take a signed 5 bit immediate. case Mips::BI__builtin_msa_ceqi_b: case Mips::BI__builtin_msa_ceqi_h: @@ -173,7 +238,11 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_mini_s_b: case Mips::BI__builtin_msa_mini_s_h: case Mips::BI__builtin_msa_mini_s_w: - case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15; break; + case Mips::BI__builtin_msa_mini_s_d: + i = 1; + l = -16; + u = 15; + break; // These intrinsics take an unsigned 8 bit immediate. case Mips::BI__builtin_msa_andi_b: case Mips::BI__builtin_msa_nori_b: @@ -181,53 +250,161 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { case Mips::BI__builtin_msa_shf_b: case Mips::BI__builtin_msa_shf_h: case Mips::BI__builtin_msa_shf_w: - case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255; break; + case Mips::BI__builtin_msa_xori_b: + i = 1; + l = 0; + u = 255; + break; case Mips::BI__builtin_msa_bseli_b: case Mips::BI__builtin_msa_bmnzi_b: - case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255; break; + case Mips::BI__builtin_msa_bmzi_b: + i = 2; + l = 0; + u = 255; + break; // df/n format // These intrinsics take an unsigned 4 bit immediate. case Mips::BI__builtin_msa_copy_s_b: case Mips::BI__builtin_msa_copy_u_b: case Mips::BI__builtin_msa_insve_b: - case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break; - case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break; + case Mips::BI__builtin_msa_splati_b: + i = 1; + l = 0; + u = 15; + break; + case Mips::BI__builtin_msa_sldi_b: + i = 2; + l = 0; + u = 15; + break; // These intrinsics take an unsigned 3 bit immediate. case Mips::BI__builtin_msa_copy_s_h: case Mips::BI__builtin_msa_copy_u_h: case Mips::BI__builtin_msa_insve_h: - case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break; - case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break; + case Mips::BI__builtin_msa_splati_h: + i = 1; + l = 0; + u = 7; + break; + case Mips::BI__builtin_msa_sldi_h: + i = 2; + l = 0; + u = 7; + break; // These intrinsics take an unsigned 2 bit immediate. case Mips::BI__builtin_msa_copy_s_w: case Mips::BI__builtin_msa_copy_u_w: case Mips::BI__builtin_msa_insve_w: - case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break; - case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break; + case Mips::BI__builtin_msa_splati_w: + i = 1; + l = 0; + u = 3; + break; + case Mips::BI__builtin_msa_sldi_w: + i = 2; + l = 0; + u = 3; + break; // These intrinsics take an unsigned 1 bit immediate. case Mips::BI__builtin_msa_copy_s_d: case Mips::BI__builtin_msa_copy_u_d: case Mips::BI__builtin_msa_insve_d: - case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break; - case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break; + case Mips::BI__builtin_msa_splati_d: + i = 1; + l = 0; + u = 1; + break; + case Mips::BI__builtin_msa_sldi_d: + i = 2; + l = 0; + u = 1; + break; // Memory offsets and immediate loads. // These intrinsics take a signed 10 bit immediate. - case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break; + case Mips::BI__builtin_msa_ldi_b: + i = 0; + l = -128; + u = 255; + break; case Mips::BI__builtin_msa_ldi_h: case Mips::BI__builtin_msa_ldi_w: - case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break; - case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1; break; - case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2; break; - case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4; break; - case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8; break; - case Mips::BI__builtin_msa_ldr_d: i = 1; l = -4096; u = 4088; m = 8; break; - case Mips::BI__builtin_msa_ldr_w: i = 1; l = -2048; u = 2044; m = 4; break; - case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1; break; - case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2; break; - case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4; break; - case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8; break; - case Mips::BI__builtin_msa_str_d: i = 2; l = -4096; u = 4088; m = 8; break; - case Mips::BI__builtin_msa_str_w: i = 2; l = -2048; u = 2044; m = 4; break; + case Mips::BI__builtin_msa_ldi_d: + i = 0; + l = -512; + u = 511; + break; + case Mips::BI__builtin_msa_ld_b: + i = 1; + l = -512; + u = 511; + m = 1; + break; + case Mips::BI__builtin_msa_ld_h: + i = 1; + l = -1024; + u = 1022; + m = 2; + break; + case Mips::BI__builtin_msa_ld_w: + i = 1; + l = -2048; + u = 2044; + m = 4; + break; + case Mips::BI__builtin_msa_ld_d: + i = 1; + l = -4096; + u = 4088; + m = 8; + break; + case Mips::BI__builtin_msa_ldr_d: + i = 1; + l = -4096; + u = 4088; + m = 8; + break; + case Mips::BI__builtin_msa_ldr_w: + i = 1; + l = -2048; + u = 2044; + m = 4; + break; + case Mips::BI__builtin_msa_st_b: + i = 2; + l = -512; + u = 511; + m = 1; + break; + case Mips::BI__builtin_msa_st_h: + i = 2; + l = -1024; + u = 1022; + m = 2; + break; + case Mips::BI__builtin_msa_st_w: + i = 2; + l = -2048; + u = 2044; + m = 4; + break; + case Mips::BI__builtin_msa_st_d: + i = 2; + l = -4096; + u = 4088; + m = 8; + break; + case Mips::BI__builtin_msa_str_d: + i = 2; + l = -4096; + u = 4088; + m = 8; + break; + case Mips::BI__builtin_msa_str_w: + i = 2; + l = -2048; + u = 2044; + m = 4; + break; } if (!m) diff --git a/clang/lib/Sema/SemaSystemZ.cpp b/clang/lib/Sema/SemaSystemZ.cpp index 717093b066..2ee91459ec 100644 --- a/clang/lib/Sema/SemaSystemZ.cpp +++ b/clang/lib/Sema/SemaSystemZ.cpp @@ -36,12 +36,21 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, // range check them here. unsigned i = 0, l = 0, u = 0; switch (BuiltinID) { - default: return false; - case SystemZ::BI__builtin_s390_lcbb: i = 1; l = 0; u = 15; break; + default: + return false; + case SystemZ::BI__builtin_s390_lcbb: + i = 1; + l = 0; + u = 15; + break; case SystemZ::BI__builtin_s390_verimb: case SystemZ::BI__builtin_s390_verimh: case SystemZ::BI__builtin_s390_verimf: - case SystemZ::BI__builtin_s390_verimg: i = 3; l = 0; u = 255; break; + case SystemZ::BI__builtin_s390_verimg: + i = 3; + l = 0; + u = 255; + break; case SystemZ::BI__builtin_s390_vfaeb: case SystemZ::BI__builtin_s390_vfaeh: case SystemZ::BI__builtin_s390_vfaef: @@ -53,16 +62,36 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, case SystemZ::BI__builtin_s390_vfaezf: case SystemZ::BI__builtin_s390_vfaezbs: case SystemZ::BI__builtin_s390_vfaezhs: - case SystemZ::BI__builtin_s390_vfaezfs: i = 2; l = 0; u = 15; break; + case SystemZ::BI__builtin_s390_vfaezfs: + i = 2; + l = 0; + u = 15; + break; case SystemZ::BI__builtin_s390_vfisb: case SystemZ::BI__builtin_s390_vfidb: return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 15) || SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 15); case SystemZ::BI__builtin_s390_vftcisb: - case SystemZ::BI__builtin_s390_vftcidb: i = 1; l = 0; u = 4095; break; - case SystemZ::BI__builtin_s390_vlbb: i = 1; l = 0; u = 15; break; - case SystemZ::BI__builtin_s390_vpdi: i = 2; l = 0; u = 15; break; - case SystemZ::BI__builtin_s390_vsldb: i = 2; l = 0; u = 15; break; + case SystemZ::BI__builtin_s390_vftcidb: + i = 1; + l = 0; + u = 4095; + break; + case SystemZ::BI__builtin_s390_vlbb: + i = 1; + l = 0; + u = 15; + break; + case SystemZ::BI__builtin_s390_vpdi: + i = 2; + l = 0; + u = 15; + break; + case SystemZ::BI__builtin_s390_vsldb: + i = 2; + l = 0; + u = 15; + break; case SystemZ::BI__builtin_s390_vstrcb: case SystemZ::BI__builtin_s390_vstrch: case SystemZ::BI__builtin_s390_vstrcf: @@ -74,19 +103,47 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, case SystemZ::BI__builtin_s390_vstrcfs: case SystemZ::BI__builtin_s390_vstrczbs: case SystemZ::BI__builtin_s390_vstrczhs: - case SystemZ::BI__builtin_s390_vstrczfs: i = 3; l = 0; u = 15; break; - case SystemZ::BI__builtin_s390_vmslg: i = 3; l = 0; u = 15; break; + case SystemZ::BI__builtin_s390_vstrczfs: + i = 3; + l = 0; + u = 15; + break; + case SystemZ::BI__builtin_s390_vmslg: + i = 3; + l = 0; + u = 15; + break; case SystemZ::BI__builtin_s390_vfminsb: case SystemZ::BI__builtin_s390_vfmaxsb: case SystemZ::BI__builtin_s390_vfmindb: - case SystemZ::BI__builtin_s390_vfmaxdb: i = 2; l = 0; u = 15; break; - case SystemZ::BI__builtin_s390_vsld: i = 2; l = 0; u = 7; break; - case SystemZ::BI__builtin_s390_vsrd: i = 2; l = 0; u = 7; break; + case SystemZ::BI__builtin_s390_vfmaxdb: + i = 2; + l = 0; + u = 15; + break; + case SystemZ::BI__builtin_s390_vsld: + i = 2; + l = 0; + u = 7; + break; + case SystemZ::BI__builtin_s390_vsrd: + i = 2; + l = 0; + u = 7; + break; case SystemZ::BI__builtin_s390_vclfnhs: case SystemZ::BI__builtin_s390_vclfnls: case SystemZ::BI__builtin_s390_vcfn: - case SystemZ::BI__builtin_s390_vcnf: i = 1; l = 0; u = 15; break; - case SystemZ::BI__builtin_s390_vcrnfs: i = 2; l = 0; u = 15; break; + case SystemZ::BI__builtin_s390_vcnf: + i = 1; + l = 0; + u = 15; + break; + case SystemZ::BI__builtin_s390_vcrnfs: + i = 2; + l = 0; + u = 15; + break; } return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u); } `````````` </details> https://github.com/llvm/llvm-project/pull/93179 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits