https://github.com/brendandahl created https://github.com/llvm/llvm-project/pull/93272
Specified at: https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md Note: the current spec has f16x8.extract_lane as opcode 0x124, but this is incorrect and will be changed to 0x121 soon. >From ee046630b80786b920b5e7d0742c27443d3ea2b0 Mon Sep 17 00:00:00 2001 From: Brendan Dahl <brendan.d...@gmail.com> Date: Thu, 23 May 2024 21:04:31 +0000 Subject: [PATCH] [WebAssembly] Implement prototype f16x8.extract_lane instruction. Specified at: https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md Note: the current spec has f16x8.extract_lane as opcode 0x124, but this is incorrect and will be changed to 0x121 soon. --- clang/include/clang/Basic/BuiltinsWebAssembly.def | 1 + clang/lib/CodeGen/CGBuiltin.cpp | 6 ++++++ clang/test/CodeGen/builtins-wasm.c | 6 ++++++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 4 ++++ .../WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h | 2 ++ llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 4 +++- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 9 +++++++++ llvm/test/CodeGen/WebAssembly/half-precision.ll | 8 ++++++++ llvm/test/MC/WebAssembly/simd-encodings.s | 3 +++ 9 files changed, 42 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def index dbe79aa39190d..fd8c1b480d6da 100644 --- a/clang/include/clang/Basic/BuiltinsWebAssembly.def +++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def @@ -194,6 +194,7 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f" TARGET_BUILTIN(__builtin_wasm_loadf16_f32, "fh*", "nU", "half-precision") TARGET_BUILTIN(__builtin_wasm_storef16_f32, "vfh*", "n", "half-precision") TARGET_BUILTIN(__builtin_wasm_splat_f16x8, "V8hf", "nc", "half-precision") +TARGET_BUILTIN(__builtin_wasm_extract_lane_f16x8, "fV8hi", "nc", "half-precision") // Reference Types builtins // Some builtins are custom type-checked - see 't' as part of the third argument, diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 91083c1cfae96..0549afa12e430 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -21235,6 +21235,12 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_splat_f16x8); return Builder.CreateCall(Callee, {Val}); } + case WebAssembly::BI__builtin_wasm_extract_lane_f16x8: { + Value *Vector = EmitScalarExpr(E->getArg(0)); + Value *Index = EmitScalarExpr(E->getArg(1)); + Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_extract_lane_f16x8); + return Builder.CreateCall(Callee, {Vector, Index}); + } case WebAssembly::BI__builtin_wasm_table_get: { assert(E->getArg(0)->getType()->isArrayType()); Value *Table = EmitArrayToPointerDecay(E->getArg(0)).emitRawPointer(*this); diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index 76c6305d422a2..93a6ab06081c9 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -819,6 +819,12 @@ f16x8 splat_f16x8(float a) { // WEBASSEMBLY-NEXT: ret <8 x half> %0 return __builtin_wasm_splat_f16x8(a); } + +float extract_lane_f16x8(f16x8 a, int i) { + // WEBASSEMBLY: %0 = tail call float @llvm.wasm.extract.lane.f16x8(<8 x half> %a, i32 %i) + // WEBASSEMBLY-NEXT: ret float %0 + return __builtin_wasm_extract_lane_f16x8(a, i); +} __externref_t externref_null() { return __builtin_wasm_ref_null_extern(); // WEBASSEMBLY: tail call ptr addrspace(10) @llvm.wasm.ref.null.extern() diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td index c950b33182689..237f268784bb0 100644 --- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td +++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td @@ -341,6 +341,10 @@ def int_wasm_splat_f16x8: DefaultAttrsIntrinsic<[llvm_v8f16_ty], [llvm_float_ty], [IntrNoMem, IntrSpeculatable]>; +def int_wasm_extract_lane_f16x8: + DefaultAttrsIntrinsic<[llvm_float_ty], + [llvm_v8f16_ty, llvm_i32_ty], + [IntrNoMem, IntrSpeculatable]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h index d4e9fb057c44d..34502170a5c71 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -345,6 +345,8 @@ inline bool isArgument(unsigned Opc) { case WebAssembly::ARGUMENT_v4i32_S: case WebAssembly::ARGUMENT_v2i64: case WebAssembly::ARGUMENT_v2i64_S: + case WebAssembly::ARGUMENT_v8f16: + case WebAssembly::ARGUMENT_v8f16_S: case WebAssembly::ARGUMENT_v4f32: case WebAssembly::ARGUMENT_v4f32_S: case WebAssembly::ARGUMENT_v2f64: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 3524abba8990a..443558537da24 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -62,7 +62,7 @@ MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const { const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16, - MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64}) + MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16}) if (TRI->isTypeLegalForClass(*TRC, T)) return T; LLVM_DEBUG(errs() << "Unknown type for register number: " << RegNo); @@ -662,6 +662,8 @@ void WebAssemblyAsmPrinter::emitInstruction(const MachineInstr *MI) { case WebAssembly::ARGUMENT_v4f32_S: case WebAssembly::ARGUMENT_v2f64: case WebAssembly::ARGUMENT_v2f64_S: + case WebAssembly::ARGUMENT_v8f16: + case WebAssembly::ARGUMENT_v8f16_S: // These represent values which are live into the function entry, so there's // no instruction to emit. break; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index bb898e7bebd3a..558e3d859dcd8 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -52,6 +52,7 @@ defm "" : ARGUMENT<V128, v4i32>; defm "" : ARGUMENT<V128, v2i64>; defm "" : ARGUMENT<V128, v4f32>; defm "" : ARGUMENT<V128, v2f64>; +defm "" : ARGUMENT<V128, v8f16>; // Constrained immediate argument types. Allow any value from the minimum signed // value to the maximum unsigned value for the lane size. @@ -659,6 +660,14 @@ def : Pat< (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; +defm EXTRACT_LANE_F16x8 : + HALF_PRECISION_I<(outs F32:$dst), (ins V128:$vec, vec_i8imm_op:$idx), + (outs), (ins vec_i8imm_op:$idx), + [(set (f32 F32:$dst), (int_wasm_extract_lane_f16x8 + (v8f16 V128:$vec), (i32 LaneIdx16:$idx)))], + "f16x8.extract_lane\t$dst, $vec, $idx", + "f16x8.extract_lane\t$idx", 0x121>; + // Replace lane value: replace_lane multiclass ReplaceLane<Vec vec, bits<32> simdop> { defm REPLACE_LANE_#vec : diff --git a/llvm/test/CodeGen/WebAssembly/half-precision.ll b/llvm/test/CodeGen/WebAssembly/half-precision.ll index eee5bf8b8c48a..d9d3f6be800fd 100644 --- a/llvm/test/CodeGen/WebAssembly/half-precision.ll +++ b/llvm/test/CodeGen/WebAssembly/half-precision.ll @@ -27,3 +27,11 @@ define <8 x half> @splat_v8f16(float %x) { %v = call <8 x half> @llvm.wasm.splat.f16x8(float %x) ret <8 x half> %v } + +; CHECK-LABEL: extract_lane_v8f16: +; CHECK: f16x8.extract_lane $push0=, $0, 1 +; CHECK-NEXT: return $pop0 +define float @extract_lane_v8f16(<8 x half> %v) { + %r = call float @llvm.wasm.extract.lane.f16x8(<8 x half> %v, i32 1) + ret float %r +} diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s index c23a9d1958099..d397188a9882e 100644 --- a/llvm/test/MC/WebAssembly/simd-encodings.s +++ b/llvm/test/MC/WebAssembly/simd-encodings.s @@ -848,4 +848,7 @@ main: # CHECK: f16x8.splat # encoding: [0xfd,0xa0,0x02] f16x8.splat + # CHECK: f16x8.extract_lane 1 # encoding: [0xfd,0xa1,0x02,0x01] + f16x8.extract_lane 1 + end_function _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
