================
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+ switch (Constraint[1]) {
+ default:
+ break;
+ case 'R':
+ if (VT == MVT::i8 || VT == MVT::i1)
+ return std::make_pair(0U, &X86::GR8RegClass);
+ if (VT == MVT::i16)
+ return std::make_pair(0U, &X86::GR16RegClass);
+ if (VT == MVT::i32 || VT == MVT::f32 ||
+ (!VT.isVector() && !Subtarget.is64Bit()))
+ return std::make_pair(0U, &X86::GR32RegClass);
----------------
KanRobert wrote:
The predicate is incorrect. EGPR is not supported in 32-bit mode.
https://github.com/llvm/llvm-project/pull/92338
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