[clang] [llvm] [AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Matt Arsenault via cfe-commits]

================
@@ -1208,7 +1225,7 @@ The AMDGPU backend implements the following LLVM IR 
intrinsics.
                                                    the output.
 
   llvm.amdgcn.sdot2                                Provides direct access to 
v_dot2_i32_i16 across targets which
-                                                   support such instructions. 
This performs signed dot product
+                                                   upport such instructions. 
This performs signed dot product
----------------
arsenm wrote:

Stray typo introduced 

https://github.com/llvm/llvm-project/pull/89217
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