llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-codegen @llvm/pr-subscribers-clang-driver Author: James Y Knight (jyknight) <details> <summary>Changes</summary> Remove support for 3DNow!, both intrinsics and builtins. This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue #<!-- -->41665. --- Patch is 130.16 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/96246.diff 32 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+17) - (modified) clang/include/clang/Basic/BuiltinsX86.def (-30) - (modified) clang/include/clang/Driver/Options.td (+6-4) - (modified) clang/lib/Basic/Targets/X86.cpp (+5-24) - (modified) clang/lib/Basic/Targets/X86.h (+2-8) - (modified) clang/lib/CodeGen/CGBuiltin.cpp (-8) - (modified) clang/lib/Driver/ToolChains/Arch/X86.cpp (+13) - (modified) clang/lib/Headers/mm3dnow.h (+4-139) - (modified) clang/lib/Headers/x86intrin.h (-4) - (removed) clang/test/CodeGen/X86/3dnow-builtins.c (-181) - (modified) clang/test/CodeGen/builtins-x86.c (+1-31) - (modified) clang/test/Driver/x86-target-features.c (+7-2) - (modified) clang/test/Headers/mm3dnow.c (+3-6) - (modified) clang/test/Preprocessor/predefined-arch-macros.c (-88) - (modified) clang/test/Preprocessor/x86_target_features.c (+2-2) - (modified) llvm/docs/ReleaseNotes.rst (+3) - (modified) llvm/include/llvm/IR/IntrinsicsX86.td (-79) - (modified) llvm/lib/Target/X86/X86.td (+10-17) - (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+1-1) - (modified) llvm/lib/Target/X86/X86Instr3DNow.td (+37-50) - (modified) llvm/lib/Target/X86/X86InstrPredicates.td (-3) - (modified) llvm/lib/Target/X86/X86Schedule.td (+1-1) - (modified) llvm/lib/Target/X86/X86ScheduleZnver3.td (+1-1) - (modified) llvm/lib/Target/X86/X86ScheduleZnver4.td (+1-1) - (modified) llvm/lib/Target/X86/X86Subtarget.cpp (+1-1) - (modified) llvm/lib/Target/X86/X86Subtarget.h (+5-17) - (removed) llvm/test/CodeGen/X86/3dnow-intrinsics.ll (-896) - (removed) llvm/test/CodeGen/X86/commute-3dnow.ll (-270) - (modified) llvm/test/CodeGen/X86/expand-vr64-gr64-copy.mir (+7-10) - (modified) llvm/test/CodeGen/X86/pr35982.ll (-45) - (modified) llvm/test/CodeGen/X86/prefetch.ll (+3-20) - (removed) llvm/test/CodeGen/X86/stack-folding-3dnow.ll (-387) ``````````diff diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 36e23981cc5df..cfe3526283d69 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -936,6 +936,23 @@ X86 Support ^^^^^^^^^^^ - Remove knl/knm specific ISA supports: AVX512PF, AVX512ER, PREFETCHWT1 +- Support has been removed for the AMD "3DNow!" instruction-set. + Neither modern AMD CPUs, nor any Intel CPUs implement these + instructions, and they were never widely used. + * The options ``-m3dnow`` and ``-m3dnowa`` are no longer honored, and will emit a warning if used. + * The macros ``__3dNOW__`` and ``__3dNOW_A__`` are no longer ever set by the compiler. + * The header ``<mm3dnow.h>`` still exists, but all of the the 3dNow + intrinsic functions have been removed: ``_m_femms``, + ``_m_pavgusb``, ``_m_pf2id``, ``_m_pfacc``, ``_m_pfadd``, + ``_m_pfcmpeq``, ``_m_pfcmpge``, ``_m_pfcmpgt``, ``_m_pfmax``, + ``_m_pfmin``, ``_m_pfmul``, ``_m_pfrcp``, ``_m_pfrcpit1``, + ``_m_pfrcpit2``, ``_m_pfrsqrt``, ``_m_pfrsqrtit1``, ``_m_pfsub``, + ``_m_pfsubr``, ``_m_pi2fd``, ``_m_pmulhrw``, ``_m_pf2iw``, + ``_m_pfnacc``, ``_m_pfpnacc``, ``_m_pi2fw``, ``_m_pswapdsf``, + ``_m_pswapdsi`` + * The compiler builtins (``__builtin_ia32_femms``, and so on) + corresponding to each of the above intrinsics have been removed. + Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 7074479786b97..a85e7918f4d7e 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -37,36 +37,6 @@ TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "") TARGET_BUILTIN(__builtin_ia32_readeflags_u32, "Ui", "n", "") TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "") -// 3DNow! -// -TARGET_BUILTIN(__builtin_ia32_femms, "v", "n", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pavgusb, "V8cV8cV8c", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pf2id, "V2iV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfacc, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfadd, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfcmpeq, "V2iV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfcmpge, "V2iV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfcmpgt, "V2iV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfmax, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfmin, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfmul, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfrcp, "V2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfrcpit1, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfrcpit2, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfrsqrt, "V2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfrsqit1, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfsub, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pfsubr, "V2fV2fV2f", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pi2fd, "V2fV2i", "ncV:64:", "3dnow") -TARGET_BUILTIN(__builtin_ia32_pmulhrw, "V4sV4sV4s", "ncV:64:", "3dnow") -// 3DNow! Extensions (3dnowa). -TARGET_BUILTIN(__builtin_ia32_pf2iw, "V2iV2f", "ncV:64:", "3dnowa") -TARGET_BUILTIN(__builtin_ia32_pfnacc, "V2fV2fV2f", "ncV:64:", "3dnowa") -TARGET_BUILTIN(__builtin_ia32_pfpnacc, "V2fV2fV2f", "ncV:64:", "3dnowa") -TARGET_BUILTIN(__builtin_ia32_pi2fw, "V2fV2i", "ncV:64:", "3dnowa") -TARGET_BUILTIN(__builtin_ia32_pswapdsf, "V2fV2f", "ncV:64:", "3dnowa") -TARGET_BUILTIN(__builtin_ia32_pswapdsi, "V2iV2i", "ncV:64:", "3dnowa") - // MMX // // All MMX instructions will be generated via builtins. Any MMX vector diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index bbf860aa491e1..78286fecad24f 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6094,10 +6094,6 @@ def mno_80387 : Flag<["-"], "mno-80387">, Alias<mno_x87>; def mno_fp_ret_in_387 : Flag<["-"], "mno-fp-ret-in-387">, Alias<mno_x87>; def mmmx : Flag<["-"], "mmmx">, Group<m_x86_Features_Group>; def mno_mmx : Flag<["-"], "mno-mmx">, Group<m_x86_Features_Group>; -def m3dnow : Flag<["-"], "m3dnow">, Group<m_x86_Features_Group>; -def mno_3dnow : Flag<["-"], "mno-3dnow">, Group<m_x86_Features_Group>; -def m3dnowa : Flag<["-"], "m3dnowa">, Group<m_x86_Features_Group>; -def mno_3dnowa : Flag<["-"], "mno-3dnowa">, Group<m_x86_Features_Group>; def mamx_bf16 : Flag<["-"], "mamx-bf16">, Group<m_x86_Features_Group>; def mno_amx_bf16 : Flag<["-"], "mno-amx-bf16">, Group<m_x86_Features_Group>; def mamx_complex : Flag<["-"], "mamx-complex">, Group<m_x86_Features_Group>; @@ -6331,6 +6327,12 @@ def mvevpu : Flag<["-"], "mvevpu">, Group<m_ve_Features_Group>, def mno_vevpu : Flag<["-"], "mno-vevpu">, Group<m_ve_Features_Group>; } // let Flags = [TargetSpecific] +// Unsupported X86 feature flags (triggers a warning) +def m3dnow : Flag<["-"], "m3dnow">; +def mno_3dnow : Flag<["-"], "mno-3dnow">; +def m3dnowa : Flag<["-"], "m3dnowa">; +def mno_3dnowa : Flag<["-"], "mno-3dnowa">; + // These are legacy user-facing driver-level option spellings. They are always // aliases for options that are spelled using the more common Unix / GNU flag // style of double-dash and equals-joined flags. diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 036a655a4d073..6083be5ee698e 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -258,7 +258,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, if (Feature[0] != '+') continue; - if (Feature == "+aes") { + if (Feature == "+mmx") { + HasMMX = true; + } else if (Feature == "+aes") { HasAES = true; } else if (Feature == "+vaes") { HasVAES = true; @@ -483,13 +485,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, // for bfloat16 arithmetic operations in the front-end. HasBFloat16 = SSELevel >= SSE2; - MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) - .Case("+3dnowa", AMD3DNowAthlon) - .Case("+3dnow", AMD3DNow) - .Case("+mmx", MMX) - .Default(NoMMX3DNow); - MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); - XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) .Case("+xop", XOP) .Case("+fma4", FMA4) @@ -1025,18 +1020,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, } // Each case falls through to the previous one here. - switch (MMX3DNowLevel) { - case AMD3DNowAthlon: - Builder.defineMacro("__3dNOW_A__"); - [[fallthrough]]; - case AMD3DNow: - Builder.defineMacro("__3dNOW__"); - [[fallthrough]]; - case MMX: + if (HasMMX) { Builder.defineMacro("__MMX__"); - [[fallthrough]]; - case NoMMX3DNow: - break; } if (CPU >= CK_i486 || CPU == CK_None) { @@ -1055,8 +1040,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, bool X86TargetInfo::isValidFeatureName(StringRef Name) const { return llvm::StringSwitch<bool>(Name) - .Case("3dnow", true) - .Case("3dnowa", true) .Case("adx", true) .Case("aes", true) .Case("amx-bf16", true) @@ -1225,9 +1208,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("widekl", HasWIDEKL) .Case("lwp", HasLWP) .Case("lzcnt", HasLZCNT) - .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) - .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) - .Case("mmx", MMX3DNowLevel >= MMX) + .Case("mmx", HasMMX) .Case("movbe", HasMOVBE) .Case("movdiri", HasMOVDIRI) .Case("movdir64b", HasMOVDIR64B) diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index 9b2ae87adb2e7..2ef404dfa18c8 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -67,12 +67,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { AVX2, AVX512F } SSELevel = NoSSE; - enum MMX3DNowEnum { - NoMMX3DNow, - MMX, - AMD3DNow, - AMD3DNowAthlon - } MMX3DNowLevel = NoMMX3DNow; + bool HasMMX = false; enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP; enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 }; @@ -346,8 +341,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { return "avx512"; if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) return "avx"; - if (getTriple().getArch() == llvm::Triple::x86 && - MMX3DNowLevel == NoMMX3DNow) + if (getTriple().getArch() == llvm::Triple::x86 && !HasMMX) return "no-mmx"; return ""; } diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 931726a78dae9..54fd0de3e20ed 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -15936,14 +15936,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, return Builder.CreateCall(F, {Ops[0]}); } - // 3DNow! - case X86::BI__builtin_ia32_pswapdsf: - case X86::BI__builtin_ia32_pswapdsi: { - llvm::Type *MMXTy = llvm::Type::getX86_MMXTy(getLLVMContext()); - Ops[0] = Builder.CreateBitCast(Ops[0], MMXTy, "cast"); - llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_3dnowa_pswapd); - return Builder.CreateCall(F, Ops, "pswapd"); - } case X86::BI__builtin_ia32_rdrand16_step: case X86::BI__builtin_ia32_rdrand32_step: case X86::BI__builtin_ia32_rdrand64_step: diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp index 75f9c99d5d0bf..067d11162cb19 100644 --- a/clang/lib/Driver/ToolChains/Arch/X86.cpp +++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp @@ -312,4 +312,17 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, Features.push_back("+prefer-no-scatter"); if (Args.hasArg(options::OPT_mapx_inline_asm_use_gpr32)) Features.push_back("+inline-asm-use-gpr32"); + + // Warn for removed 3dnow support + if (const Arg *A = + Args.getLastArg(options::OPT_m3dnowa, options::OPT_mno_3dnowa, + options::OPT_mno_3dnow)) { + if (A->getOption().matches(options::OPT_m3dnowa)) + D.Diag(diag::warn_drv_clang_unsupported) << A->getAsString(Args); + } + if (const Arg *A = + Args.getLastArg(options::OPT_m3dnow, options::OPT_mno_3dnow)) { + if (A->getOption().matches(options::OPT_m3dnow)) + D.Diag(diag::warn_drv_clang_unsupported) << A->getAsString(Args); + } } diff --git a/clang/lib/Headers/mm3dnow.h b/clang/lib/Headers/mm3dnow.h index 22ab13aa33409..10049553969f2 100644 --- a/clang/lib/Headers/mm3dnow.h +++ b/clang/lib/Headers/mm3dnow.h @@ -7,151 +7,16 @@ *===-----------------------------------------------------------------------=== */ +// 3dNow intrinsics are no longer supported, and this header remains only as a +// stub for users who were including it to get to _m_prefetch or +// _m_prefetchw. Such uses should prefer x86intrin.h. + #ifndef _MM3DNOW_H_INCLUDED #define _MM3DNOW_H_INCLUDED #include <mmintrin.h> #include <prfchwintrin.h> -typedef float __v2sf __attribute__((__vector_size__(8))); - -/* Define the default attributes for the functions in this file. */ -#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("3dnow"), __min_vector_width__(64))) - -static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("3dnow"))) -_m_femms(void) { - __builtin_ia32_femms(); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pavgusb(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pavgusb((__v8qi)__m1, (__v8qi)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pf2id(__m64 __m) { - return (__m64)__builtin_ia32_pf2id((__v2sf)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfacc(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfacc((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfadd(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfadd((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfcmpeq(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfcmpeq((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfcmpge(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfcmpge((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfcmpgt(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfcmpgt((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfmax(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfmax((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfmin(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfmin((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfmul(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfmul((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfrcp(__m64 __m) { - return (__m64)__builtin_ia32_pfrcp((__v2sf)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfrcpit1(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfrcpit1((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfrcpit2(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfrcpit2((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfrsqrt(__m64 __m) { - return (__m64)__builtin_ia32_pfrsqrt((__v2sf)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfrsqrtit1(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfrsqit1((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfsub(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfsub((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfsubr(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfsubr((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pi2fd(__m64 __m) { - return (__m64)__builtin_ia32_pi2fd((__v2si)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pmulhrw(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pmulhrw((__v4hi)__m1, (__v4hi)__m2); -} - -/* Handle the 3dnowa instructions here. */ -#undef __DEFAULT_FN_ATTRS -#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("3dnowa"), __min_vector_width__(64))) - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pf2iw(__m64 __m) { - return (__m64)__builtin_ia32_pf2iw((__v2sf)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfnacc(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfnacc((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pfpnacc(__m64 __m1, __m64 __m2) { - return (__m64)__builtin_ia32_pfpnacc((__v2sf)__m1, (__v2sf)__m2); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pi2fw(__m64 __m) { - return (__m64)__builtin_ia32_pi2fw((__v2si)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pswapdsf(__m64 __m) { - return (__m64)__builtin_ia32_pswapdsf((__v2sf)__m); -} - -static __inline__ __m64 __DEFAULT_FN_ATTRS -_m_pswapdsi(__m64 __m) { - return (__m64)__builtin_ia32_pswapdsi((__v2si)__m); -} - #undef __DEFAULT_FN_ATTRS #endif diff --git a/clang/lib/Headers/x86intrin.h b/clang/lib/Headers/x86intrin.h index c20bfbb8fe46e..f42e9e580f883 100644 --- a/clang/lib/Headers/x86intrin.h +++ b/clang/lib/Headers/x86intrin.h @@ -14,10 +14,6 @@ #include <immintrin.h> -#if !defined(__SCE__) || __has_feature(modules) || defined(__3dNOW__) -#include <mm3dnow.h> -#endif - #if !defined(__SCE__) || __has_feature(modules) || defined(__PRFCHW__) #include <prfchwintrin.h> #endif diff --git a/clang/test/CodeGen/X86/3dnow-builtins.c b/clang/test/CodeGen/X86/3dnow-builtins.c deleted file mode 100644 index af754b71555c4..0000000000000 --- a/clang/test/CodeGen/X86/3dnow-builtins.c +++ /dev/null @@ -1,181 +0,0 @@ -// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=GCC -check-prefix=CHECK -// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=PS4 -check-prefix=CHECK -// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-sie-ps5 -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=PS4 -check-prefix=CHECK - - -#include <x86intrin.h> - -__m64 test_m_pavgusb(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pavgusb - // GCC-LABEL: define{{.*}} double @test_m_pavgusb - // CHECK: @llvm.x86.3dnow.pavgusb - return _m_pavgusb(m1, m2); -} - -__m64 test_m_pf2id(__m64 m) { - // PS4-LABEL: define{{.*}} i64 @test_m_pf2id - // GCC-LABEL: define{{.*}} double @test_m_pf2id - // CHECK: @llvm.x86.3dnow.pf2id - return _m_pf2id(m); -} - -__m64 test_m_pfacc(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfacc - // GCC-LABEL: define{{.*}} double @test_m_pfacc - // CHECK: @llvm.x86.3dnow.pfacc - return _m_pfacc(m1, m2); -} - -__m64 test_m_pfadd(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfadd - // GCC-LABEL: define{{.*}} double @test_m_pfadd - // CHECK: @llvm.x86.3dnow.pfadd - return _m_pfadd(m1, m2); -} - -__m64 test_m_pfcmpeq(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpeq - // GCC-LABEL: define{{.*}} double @test_m_pfcmpeq - // CHECK: @llvm.x86.3dnow.pfcmpeq - return _m_pfcmpeq(m1, m2); -} - -__m64 test_m_pfcmpge(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpge - // GCC-LABEL: define{{.*}} double @test_m_pfcmpge - // CHECK: @llvm.x86.3dnow.pfcmpge - return _m_pfcmpge(m1, m2); -} - -__m64 test_m_pfcmpgt(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpgt - // GCC-LABEL: define{{.*}} double @test_m_pfcmpgt - // CHECK: @llvm.x86.3dnow.pfcmpgt - return _m_pfcmpgt(m1, m2); -} - -__m64 test_m_pfmax(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfmax - // GCC-LABEL: define{{.*}} double @test_m_pfmax - // CHECK: @llvm.x86.3dnow.pfmax - return _m_pfmax(m1, m2); -} - -__m64 test_m_pfmin(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfmin - // GCC-LABEL: define{{.*}} double @test_m_pfmin - // CHECK: @llvm.x86.3dnow.pfmin - return _m_pfmin(m1, m2); -} - -__m64 test_m_pfmul(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfmul - // GCC-LABEL: define{{.*}} double @test_m_pfmul - // CHECK: @llvm.x86.3dnow.pfmul - return _m_pfmul(m1, m2); -} - -__m64 test_m_pfrcp(__m64 m) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfrcp - // GCC-LABEL: define{{.*}} double @test_m_pfrcp - // CHECK: @llvm.x86.3dnow.pfrcp - return _m_pfrcp(m); -} - -__m64 test_m_pfrcpit1(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit1 - // GCC-LABEL: define{{.*}} double @test_m_pfrcpit1 - // CHECK: @llvm.x86.3dnow.pfrcpit1 - return _m_pfrcpit1(m1, m2); -} - -__m64 test_m_pfrcpit2(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit2 - // GCC-LABEL: define{{.*}} double @test_m_pfrcpit2 - // CHECK: @llvm.x86.3dnow.pfrcpit2 - return _m_pfrcpit2(m1, m2); -} - -__m64 test_m_pfrsqrt(__m64 m) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrt - // GCC-LABEL: define{{.*}} double @test_m_pfrsqrt - // CHECK: @llvm.x86.3dnow.pfrsqrt - return _m_pfrsqrt(m); -} - -__m64 test_m_pfrsqrtit1(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrtit1 - // GCC-LABEL: define{{.*}} double @test_m_pfrsqrtit1 - // CHECK: @llvm.x86.3dnow.pfrsqit1 - return _m_pfrsqrtit1(m1, m2); -} - -__m64 test_m_pfsub(__m64 m1, __m64 m2) { - // PS4-LABEL: define{{.*}} i64 @test_m_pfsub - // GCC-LABEL: define{{.*}} double @test_m_pfsub - // CHECK: @llvm.x86.3dnow.pfsub - return _m_pfsub(m1, m2); -} - -__m64 test_m_pfsubr(__m64 m1, __m64 m2) { - ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/96246 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
