Author: Anton Sidorenko Date: 2024-06-21T11:40:10+03:00 New Revision: d59a4cac5fe6c05da0e9088aad8f94c207423c36
URL: https://github.com/llvm/llvm-project/commit/d59a4cac5fe6c05da0e9088aad8f94c207423c36 DIFF: https://github.com/llvm/llvm-project/commit/d59a4cac5fe6c05da0e9088aad8f94c207423c36.diff LOG: [RISCV] Add Syntacore SCR3 processor definition (#95953) Syntacore SCR3 is a microcontroller-class processor core. Overview: https://syntacore.com/products/scr3 This PR introduces two CPUs: * 'syntacore-scr3-rv32' which is rv32imc * 'syntacore-scr3-rv64' which is rv64imac --------- Co-authored-by: Dmitrii Petrov <dmitrii.pet...@syntacore.com> Added: Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note.c llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 41c257bc559ed..26bcda6468dd2 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -358,3 +358,26 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s +// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32" +// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+m" +// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zicsr" +// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zifencei" +// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-abi" "ilp32" + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s +// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s +// MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+m" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+a" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zicsr" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zifencei" +// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-abi" "lp64" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s +// MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 59d3aaa122dbe..1a9063ee5a257 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -81,16 +81,16 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}} +// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}} // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, generic, rocket, sifive-7-series{{$}} // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 61f63c59cbc57..76356dd76f1d2 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -183,6 +183,7 @@ Changes to the RISC-V Backend * Zabha is no longer experimental. * B (the collection of the Zba, Zbb, Zbs extensions) is supported. * Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march. +* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 0348b75449836..6d71cb6a41423 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", FeatureStdExtC], [TuneNoDefaultUnroll]>; +def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", + NoSchedModel, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtC], + [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + +def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtC], + [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, [Feature64Bit, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
