Author: Philip Reames Date: 2024-06-24T08:32:28-07:00 New Revision: f985a8826bfa4ca3d23e654185de35e30ea6dc79
URL: https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79 DIFF: https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79.diff LOG: Revert "[RISCV] Remove experimental from Ztso. (#96465)" This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See discussion on review thread. Added: Modified: clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll llvm/test/CodeGen/RISCV/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-load-store.ll llvm/test/CodeGen/RISCV/atomic-rmw.ll llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll llvm/test/CodeGen/RISCV/attributes.ll llvm/test/CodeGen/RISCV/module-elf-flags.ll llvm/test/MC/RISCV/Ztso.s llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/elf-flags.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index c3c471c4bc396..ffd92e1f398c4 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -365,30 +365,24 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s // RV32-ZFHMIN: "-target-feature" "+zfhmin" -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr' +// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso' // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr' +// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s -// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.1) +// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7' +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'ztso' (this compiler supports 0.1) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s -// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr" - -// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso1p0 -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s -// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s -// RV32-ZTSO: "-target-feature" "+ztso" +// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso" // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 46a61e3c0afc7..d7935af532dfa 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1650,13 +1650,13 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} -// RUN: %clang --target=riscv32-unknown-linux-gnu \ -// RUN: -march=rv32iztso1p0 -E -dM %s \ +// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32iztso0p1 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s -// RUN: %clang --target=riscv64-unknown-linux-gnu \ -// RUN: -march=rv64iztso1p0 -E -dM %s \ +// RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64iztso0p1 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s -// CHECK-ZTSO-EXT: __riscv_ztso 1000000{{$}} +// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32ifzvfbfmin1p0 -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 8ce841103a5b9..152849a01c37f 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -178,7 +178,6 @@ on support follow. ``Zks`` Supported ``Zkt`` Supported ``Zmmul`` Supported - ``Ztso`` Supported ``Zvbb`` Assembly Support ``Zvbc`` Assembly Support ``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported @@ -278,6 +277,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. +``experimental-ztso`` + LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 2abb0fd956b64..76356dd76f1d2 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -184,7 +184,6 @@ Changes to the RISC-V Backend * B (the collection of the Zba, Zbb, Zbs extensions) is supported. * Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march. * ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added. -* Ztso is no longer experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e37b0ada54f49..a5e34def81c85 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -196,8 +196,8 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, "'A' (Atomic Instructions)">; def FeatureStdExtZtso - : RISCVExtension<"ztso", 1, 0, - "'Ztso' (Memory Model - Total Store Order)">; + : RISCVExperimentalExtension<"ztso", 0, 1, + "'Ztso' (Memory Model - Total Store Order)">; def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, AssemblerPredicate<(all_of FeatureStdExtZtso), "'Ztso' (Memory Model - Total Store Order)">; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll index aecc66da21f6c..f41a89fc45940 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll @@ -3,13 +3,13 @@ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a -global-isel -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -global-isel -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -global-isel -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,TSO %s ; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv64 -mattr=+a -global-isel -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -global-isel -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -global-isel -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,TSO %s define void @fence_acquire() nounwind { diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll index e336246b450a4..341d4c90e638a 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll @@ -5,9 +5,9 @@ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-WMO-ZACAS %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+zacas -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-TSO-ZACAS %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s @@ -17,11 +17,11 @@ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zacas,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-WMO-ZABHA %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zacas -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO-ZACAS %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zacas,+zabha -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+zacas,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-TSO-ZABHA %s define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { diff --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll index 7103345ce7bc2..07e0cd066331a 100644 --- a/llvm/test/CodeGen/RISCV/atomic-fence.ll +++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll @@ -3,13 +3,13 @@ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,TSO %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,WMO %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,TSO %s define void @fence_acquire() nounwind { diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll index 5bcecbb7bcf83..2d1fc21cda89b 100644 --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -3,24 +3,24 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO-TRAILING-FENCE %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO-TRAILING-FENCE %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO-TRAILING-FENCE %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll index c7c9c339a8880..e95846b720097 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -3,31 +3,31 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-WMO,RV32IA-WMO-NOZACAS %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-NOZACAS,RV32IA-TSO,RV32IA-TSO-NOZACAS %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS,RV64IA-WMO,RV64IA-WMO-NOZACAS %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-NOZACAS,RV64IA-TSO,RV64IA-TSO-NOZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-WMO,RV32IA-WMO-ZACAS %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+zacas -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZACAS,RV32IA-TSO,RV32IA-TSO-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO,RV64IA-WMO-ZACAS %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zacas -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO,RV64IA-TSO-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-NOZACAS %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zabha -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-NOZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-ZACAS %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zabha,+zacas -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+zabha,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-ZACAS %s define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index 634ed45044ee2..a5a2ae79966c3 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -3,13 +3,13 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IA %s diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 9a3405effb93a..f20f6f7c6f94e 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -211,7 +211,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s ; RUN: llc -mtriple=riscv64 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAMA16B %s ; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s -; RUN: llc -mtriple=riscv64 -mattr=+ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s ; RUN: llc -mtriple=riscv64 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV64ZAAMO %s ; RUN: llc -mtriple=riscv64 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s @@ -492,7 +492,7 @@ ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0" ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" -; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0" +; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1" ; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0" ; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc1p0" ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0" diff --git a/llvm/test/CodeGen/RISCV/module-elf-flags.ll b/llvm/test/CodeGen/RISCV/module-elf-flags.ll index b260284b22c0e..1b4bc9fd5466c 100644 --- a/llvm/test/CodeGen/RISCV/module-elf-flags.ll +++ b/llvm/test/CodeGen/RISCV/module-elf-flags.ll @@ -10,4 +10,4 @@ define i32 @addi(i32 %a) { !llvm.module.flags = !{!0} !0 = !{i32 6, !"riscv-isa", !1} -!1 = !{!"rv64i2p1_c2p0_ztso1p0"} +!1 = !{!"rv64i2p1_c2p0_ztso0p1"} diff --git a/llvm/test/MC/RISCV/Ztso.s b/llvm/test/MC/RISCV/Ztso.s index 06b1030fca7ef..fb4f08efe51e3 100644 --- a/llvm/test/MC/RISCV/Ztso.s +++ b/llvm/test/MC/RISCV/Ztso.s @@ -1,5 +1,5 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+ztso -riscv-no-aliases 2>&1 | FileCheck %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+ztso -riscv-no-aliases 2>&1 | FileCheck %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s # Note: Ztso doesn't add or remove any instructions, so this is basically # just checking that a) we accepted the attribute name, and b) codegen did diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 423ab9b19ece0..e8029ba71cb69 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -276,8 +276,8 @@ .attribute arch, "rv32izawrs1p0" # CHECK: attribute 5, "rv32i2p1_zawrs1p0" -.attribute arch, "rv32iztso1p0" -# CHECK: attribute 5, "rv32i2p1_ztso1p0" +.attribute arch, "rv32iztso0p1" +# CHECK: attribute 5, "rv32i2p1_ztso0p1" .attribute arch, "rv32izicsr2p0" # CHECK: attribute 5, "rv32i2p1_zicsr2p0" diff --git a/llvm/test/MC/RISCV/elf-flags.s b/llvm/test/MC/RISCV/elf-flags.s index c1d9d00c08894..ee59e068e2289 100644 --- a/llvm/test/MC/RISCV/elf-flags.s +++ b/llvm/test/MC/RISCV/elf-flags.s @@ -10,8 +10,8 @@ # RUN: llvm-mc -triple=riscv64 -mattr=+e -filetype=obj < %s \ # RUN: | llvm-readobj --file-headers - \ # RUN: | FileCheck -check-prefix=CHECK-RVE %s -# RUN: llvm-mc -triple=riscv32 -mattr=+ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s -# RUN: llvm-mc -triple=riscv64 -mattr=+ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s +# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s +# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s # CHECK-RVI: Flags [ (0x0) # CHECK-RVI-NEXT: ] diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index e69723dfd975d..60bbf01c6276b 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -554,52 +554,50 @@ TEST(ParseArchString, RejectsDuplicateExtensionNames) { TEST(ParseArchString, RejectsExperimentalExtensionsIfNotEnableExperimentalExtension) { EXPECT_EQ( - toString( - RISCVISAInfo::parseArchString("rv64izfbfmin", false).takeError()), + toString(RISCVISAInfo::parseArchString("rv64iztso", false).takeError()), "requires '-menable-experimental-extensions' for experimental extension " - "'zfbfmin'"); + "'ztso'"); } TEST(ParseArchString, AcceptsExperimentalExtensionsIfEnableExperimentalExtension) { - // Note: If zalasr becomes none-experimental, this test will need + // Note: If ztso becomes none-experimental, this test will need // updating (and unfortunately, it will still pass). The failure of // RejectsExperimentalExtensionsIfNotEnableExperimentalExtension will // hopefully serve as a reminder to update. - auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64izalasr", true, false); + auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64iztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_EQ(Exts.count("zalasr"), 1U); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izalasr0p1", true); + EXPECT_EQ(Exts.count("ztso"), 1U); + auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64iztso0p1", true); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); const auto &Exts2 = (*MaybeISAInfo2)->getExtensions(); EXPECT_EQ(Exts2.size(), 2UL); - EXPECT_EQ(Exts2.count("zalasr"), 1U); + EXPECT_EQ(Exts2.count("ztso"), 1U); } TEST(ParseArchString, RequiresExplicitVersionNumberForExperimentalExtensionByDefault) { EXPECT_EQ( - toString(RISCVISAInfo::parseArchString("rv64izalasr", true).takeError()), - "experimental extension requires explicit version number `zalasr`"); + toString(RISCVISAInfo::parseArchString("rv64iztso", true).takeError()), + "experimental extension requires explicit version number `ztso`"); } TEST(ParseArchString, AcceptsUnrecognizedVersionIfNotExperimentalExtensionVersionCheck) { auto MaybeISAInfo = - RISCVISAInfo::parseArchString("rv64izalasr9p9", true, false); + RISCVISAInfo::parseArchString("rv64iztso9p9", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_TRUE(Exts.at("zalasr") == (RISCVISAUtils::ExtensionVersion{9, 9})); + EXPECT_TRUE(Exts.at("ztso") == (RISCVISAUtils::ExtensionVersion{9, 9})); } TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { EXPECT_EQ( - toString( - RISCVISAInfo::parseArchString("rv64izalasr9p9", true).takeError()), - "unsupported version number 9.9 for experimental extension 'zalasr' " + toString(RISCVISAInfo::parseArchString("rv64iztso9p9", true).takeError()), + "unsupported version number 9.9 for experimental extension 'ztso' " "(this compiler supports 0.1)"); } @@ -741,16 +739,16 @@ TEST(ParseArchString, TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) { auto MaybeISAInfo1 = - RISCVISAInfo::parseArchString("rv64im_zalasr", true, false); + RISCVISAInfo::parseArchString("rv64im_ztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded()); EXPECT_THAT((*MaybeISAInfo1)->toFeatures(), - ElementsAre("+m", "+zmmul", "+experimental-zalasr")); + ElementsAre("+m", "+zmmul", "+experimental-ztso")); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString( - "rv32e_zalasr_xventanacondops", true, false); + auto MaybeISAInfo2 = + RISCVISAInfo::parseArchString("rv32e_ztso_xventanacondops", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); EXPECT_THAT((*MaybeISAInfo2)->toFeatures(), - ElementsAre("+e", "+experimental-zalasr", "+xventanacondops")); + ElementsAre("+e", "+experimental-ztso", "+xventanacondops")); } TEST(ToFeatures, UnsupportedExtensionsAreDropped) { @@ -895,8 +893,10 @@ TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) { TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) { EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbb"), "zbb"); - EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso1p0"), "ztso"); - EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso"), "ztso"); + EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso0p1"), + "experimental-ztso"); + EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso"), + "experimental-ztso"); EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zihintntl1234p4321"), ""); EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zfoo"), ""); @@ -975,7 +975,6 @@ R"(All available -march extensions for RISC-V zksed 1.0 zksh 1.0 zkt 1.0 - ztso 1.0 zvbb 1.0 zvbc 1.0 zve32f 1.0 @@ -1075,6 +1074,7 @@ Experimental extensions zicfiss 0.4 zalasr 0.1 zfbfmin 1.0 + ztso 0.1 zvfbfmin 1.0 zvfbfwma 1.0 smmpm 0.8 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
