================ @@ -89,14 +89,14 @@ def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto", "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32", - "Enable ARMv8 CRC-32 checksum instructions">; + "Enable Armv8.0-A CRC-32 checksum instructions">; // This SubtargetFeature is special. It controls only whether codegen will turn // `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The // `FEAT_PMUv3*` system registers are always available for assembly/disassembly. let UserVisibleName = "pmuv3" in def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon", "FEAT_PMUv3", - "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension">; + "Enable Armv8.0-A Code Generation for PMUv3 Performance Monitors extension">; ---------------- lenary wrote:
This feature is different to the rest. the system registers for PMUv3 are always enabled for asm/disasm, this feature just says whether some intrinsics generate system register accesses. https://github.com/llvm/llvm-project/pull/98550 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
