mehdi_amini updated this revision to Diff 83459.
mehdi_amini added a comment.
Address comments: reorganize the way ShouldAddOptNone is handled, hopefully
make it more easy to track.
Also after talking with Chandler on IRC, the source attribute "cold" does
not add the LLVM IR attribute "optsize" at O0, we add "optnone" instead.
https://reviews.llvm.org/D28404
Files:
clang/include/clang/Driver/CC1Options.td
clang/include/clang/Frontend/CodeGenOptions.def
clang/lib/CodeGen/CGOpenMPRuntime.cpp
clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/aarch64-neon-2velem.c
clang/test/CodeGen/aarch64-neon-3v.c
clang/test/CodeGen/aarch64-neon-across.c
clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
clang/test/CodeGen/aarch64-neon-fma.c
clang/test/CodeGen/aarch64-neon-intrinsics.c
clang/test/CodeGen/aarch64-neon-ldst-one.c
clang/test/CodeGen/aarch64-neon-misc.c
clang/test/CodeGen/aarch64-neon-perm.c
clang/test/CodeGen/aarch64-neon-scalar-copy.c
clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
clang/test/CodeGen/aarch64-neon-shifts.c
clang/test/CodeGen/aarch64-neon-tbl.c
clang/test/CodeGen/aarch64-neon-vcombine.c
clang/test/CodeGen/aarch64-neon-vget-hilo.c
clang/test/CodeGen/aarch64-neon-vget.c
clang/test/CodeGen/aarch64-poly64.c
clang/test/CodeGen/address-safety-attr-kasan.cpp
clang/test/CodeGen/address-safety-attr.cpp
clang/test/CodeGen/arm-crc32.c
clang/test/CodeGen/arm-neon-directed-rounding.c
clang/test/CodeGen/arm-neon-fma.c
clang/test/CodeGen/arm-neon-numeric-maxmin.c
clang/test/CodeGen/arm-neon-vcvtX.c
clang/test/CodeGen/arm-neon-vget.c
clang/test/CodeGen/arm64-lanes.c
clang/test/CodeGen/arm64_vcopy.c
clang/test/CodeGen/arm64_vdupq_n_f64.c
clang/test/CodeGen/attr-coldhot.c
clang/test/CodeGen/builtins-arm-exclusive.c
clang/test/CodeGen/builtins-arm.c
clang/test/CodeGen/builtins-arm64.c
clang/test/CodeGen/noduplicate-cxx11-test.cpp
clang/test/CodeGen/pragma-weak.c
clang/test/CodeGen/unwind-attr.c
clang/test/CodeGenCXX/apple-kext-indirect-virtual-dtor-call.cpp
clang/test/CodeGenCXX/apple-kext-no-staticinit-section.cpp
clang/test/CodeGenCXX/debug-info-global-ctor-dtor.cpp
clang/test/CodeGenCXX/optnone-templates.cpp
clang/test/CodeGenCXX/static-init-wasm.cpp
clang/test/CodeGenCXX/thunks.cpp
clang/test/CodeGenObjC/gnu-exceptions.m
clang/test/CodeGenOpenCL/amdgpu-attrs.cl
clang/test/Driver/darwin-iphone-defaults.m
Index: clang/test/Driver/darwin-iphone-defaults.m
===================================================================
--- clang/test/Driver/darwin-iphone-defaults.m
+++ clang/test/Driver/darwin-iphone-defaults.m
@@ -26,4 +26,4 @@
[I1 alloc];
}
-// CHECK: attributes [[F0]] = { noinline ssp{{.*}} }
+// CHECK: attributes [[F0]] = { noinline optnone ssp{{.*}} }
Index: clang/test/CodeGenOpenCL/amdgpu-attrs.cl
===================================================================
--- clang/test/CodeGenOpenCL/amdgpu-attrs.cl
+++ clang/test/CodeGenOpenCL/amdgpu-attrs.cl
@@ -141,26 +141,26 @@
// CHECK-NOT: "amdgpu-num-sgpr"="0"
// CHECK-NOT: "amdgpu-num-vgpr"="0"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2]] = { noinline nounwind "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2_4]] = { noinline nounwind "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[NUM_SGPR_32]] = { noinline nounwind "amdgpu-num-sgpr"="32"
-// CHECK-DAG: attributes [[NUM_VGPR_64]] = { noinline nounwind "amdgpu-num-vgpr"="64"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2]] = { noinline nounwind optnone "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2_4]] = { noinline nounwind optnone "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-num-sgpr"="32"
+// CHECK-DAG: attributes [[NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-num-vgpr"="64"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_NUM_SGPR_32]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_NUM_VGPR_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2_NUM_SGPR_32]] = { noinline nounwind "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2_NUM_VGPR_64]] = { noinline nounwind "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2_4_NUM_SGPR_32]] = { noinline nounwind "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[WAVES_PER_EU_2_4_NUM_VGPR_64]] = { noinline nounwind "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2_NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2_4_NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[WAVES_PER_EU_2_4_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_SGPR_32]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_VGPR_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_SGPR_32]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_VGPR_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_SGPR_32]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
-// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2"
+// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64_WAVES_PER_EU_2_4_NUM_SGPR_32_NUM_VGPR_64]] = { noinline nounwind optnone "amdgpu-flat-work-group-size"="32,64" "amdgpu-num-sgpr"="32" "amdgpu-num-vgpr"="64" "amdgpu-waves-per-eu"="2,4"
Index: clang/test/CodeGenObjC/gnu-exceptions.m
===================================================================
--- clang/test/CodeGenObjC/gnu-exceptions.m
+++ clang/test/CodeGenObjC/gnu-exceptions.m
@@ -32,4 +32,4 @@
log(1);
}
-// CHECK: attributes [[TF]] = { noinline "{{.*}} }
+// CHECK: attributes [[TF]] = { noinline optnone "{{.*}} }
Index: clang/test/CodeGenCXX/thunks.cpp
===================================================================
--- clang/test/CodeGenCXX/thunks.cpp
+++ clang/test/CodeGenCXX/thunks.cpp
@@ -401,5 +401,5 @@
// CHECK-OPT-LABEL: define linkonce_odr void @_ZN6Test101C3fooEv
// CHECK-OPT-LABEL: define linkonce_odr void @_ZThn8_N6Test101C3fooEv
-// CHECK-NONOPT: attributes [[NUW]] = { noinline nounwind uwtable{{.*}} }
+// CHECK-NONOPT: attributes [[NUW]] = { noinline nounwind optnone uwtable{{.*}} }
// CHECK-OPT: attributes [[NUW]] = { nounwind uwtable{{.*}} }
Index: clang/test/CodeGenCXX/static-init-wasm.cpp
===================================================================
--- clang/test/CodeGenCXX/static-init-wasm.cpp
+++ clang/test/CodeGenCXX/static-init-wasm.cpp
@@ -43,12 +43,12 @@
A theA;
-// WEBASSEMBLY32: define internal void @__cxx_global_var_init() #0 section ".text.__startup" {
+// WEBASSEMBLY32: define internal void @__cxx_global_var_init() #3 section ".text.__startup" {
// WEBASSEMBLY32: call %struct.A* @_ZN1AC1Ev(%struct.A* @theA)
-// WEBASSEMBLY32: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #0 section ".text.__startup" {
+// WEBASSEMBLY32: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #3 section ".text.__startup" {
// WEBASSEMBLY32: call void @__cxx_global_var_init()
//
-// WEBASSEMBLY64: define internal void @__cxx_global_var_init() #0 section ".text.__startup" {
+// WEBASSEMBLY64: define internal void @__cxx_global_var_init() #3 section ".text.__startup" {
// WEBASSEMBLY64: call %struct.A* @_ZN1AC1Ev(%struct.A* @theA)
-// WEBASSEMBLY64: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #0 section ".text.__startup" {
+// WEBASSEMBLY64: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #3 section ".text.__startup" {
// WEBASSEMBLY64: call void @__cxx_global_var_init()
Index: clang/test/CodeGenCXX/optnone-templates.cpp
===================================================================
--- clang/test/CodeGenCXX/optnone-templates.cpp
+++ clang/test/CodeGenCXX/optnone-templates.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -triple %itanium_abi_triple -std=c++11 -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple %itanium_abi_triple -std=c++11 -disable-O0-optnone -emit-llvm -o - | FileCheck %s
// Test optnone on template instantiations.
Index: clang/test/CodeGenCXX/debug-info-global-ctor-dtor.cpp
===================================================================
--- clang/test/CodeGenCXX/debug-info-global-ctor-dtor.cpp
+++ clang/test/CodeGenCXX/debug-info-global-ctor-dtor.cpp
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 %s -debug-info-kind=limited -triple %itanium_abi_triple -fno-use-cxa-atexit -S -emit-llvm -o - \
+// RUN: %clang_cc1 %s -debug-info-kind=limited -triple %itanium_abi_triple -fno-use-cxa-atexit -S -disable-O0-optnone -emit-llvm -o - \
// RUN: | FileCheck %s --check-prefix=CHECK-NOKEXT
-// RUN: %clang_cc1 %s -debug-info-kind=limited -triple %itanium_abi_triple -fno-use-cxa-atexit -fapple-kext -S -emit-llvm -o - \
+// RUN: %clang_cc1 %s -debug-info-kind=limited -triple %itanium_abi_triple -fno-use-cxa-atexit -fapple-kext -S -disable-O0-optnone -emit-llvm -o - \
// RUN: | FileCheck %s --check-prefix=CHECK-KEXT
class A {
Index: clang/test/CodeGenCXX/apple-kext-no-staticinit-section.cpp
===================================================================
--- clang/test/CodeGenCXX/apple-kext-no-staticinit-section.cpp
+++ clang/test/CodeGenCXX/apple-kext-no-staticinit-section.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fapple-kext -fno-rtti -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fapple-kext -fno-rtti -disable-O0-optnone -emit-llvm -o - %s | FileCheck %s
// rdar://8825235
/**
1) Normally, global object construction code ends up in __StaticInit segment of text section
Index: clang/test/CodeGenCXX/apple-kext-indirect-virtual-dtor-call.cpp
===================================================================
--- clang/test/CodeGenCXX/apple-kext-indirect-virtual-dtor-call.cpp
+++ clang/test/CodeGenCXX/apple-kext-indirect-virtual-dtor-call.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fapple-kext -fno-rtti -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fapple-kext -fno-rtti -disable-O0-optnone -emit-llvm -o - %s | FileCheck %s
// CHECK: @_ZTV5TemplIiE = internal unnamed_addr constant { [7 x i8*] } { [7 x i8*] [i8* null, i8* null, i8* bitcast (void (%struct.Templ*)* @_ZN5TemplIiED1Ev to i8*), i8* bitcast (void (%struct.Templ*)* @_ZN5TemplIiED0Ev to i8*), i8* bitcast (void (%struct.Templ*)* @_ZN5TemplIiE1fEv to i8*), i8* bitcast (void (%struct.Templ*)* @_ZN5TemplIiE1gEv to i8*), i8* null] }
Index: clang/test/CodeGen/unwind-attr.c
===================================================================
--- clang/test/CodeGen/unwind-attr.c
+++ clang/test/CodeGen/unwind-attr.c
@@ -23,7 +23,7 @@
return 0;
}
-// CHECK: attributes [[TF]] = { noinline "{{.*}} }
+// CHECK: attributes [[TF]] = { noinline optnone "{{.*}} }
// CHECK: attributes [[NUW]] = { noinline nounwind{{.*}} }
// CHECK-NOEXC: attributes [[NUW]] = { noinline nounwind{{.*}} }
Index: clang/test/CodeGen/pragma-weak.c
===================================================================
--- clang/test/CodeGen/pragma-weak.c
+++ clang/test/CodeGen/pragma-weak.c
@@ -189,4 +189,4 @@
int correct_linkage;
// CHECK: attributes [[NI]] = { noinline nounwind{{.*}} }
-// CHECK: attributes [[RN]] = { noinline nounwind readnone{{.*}} }
+// CHECK: attributes [[RN]] = { noinline nounwind optnone readnone{{.*}} }
Index: clang/test/CodeGen/noduplicate-cxx11-test.cpp
===================================================================
--- clang/test/CodeGen/noduplicate-cxx11-test.cpp
+++ clang/test/CodeGen/noduplicate-cxx11-test.cpp
@@ -17,4 +17,4 @@
}
-// CHECK: attributes [[NI]] = { noduplicate nounwind{{.*}} }
+// CHECK: attributes [[NI]] = { noduplicate {{.*}}nounwind{{.*}} }
Index: clang/test/CodeGen/builtins-arm64.c
===================================================================
--- clang/test/CodeGen/builtins-arm64.c
+++ clang/test/CodeGen/builtins-arm64.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-unknown-linux -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
void f0(void *a, void *b) {
__clear_cache(a,b);
Index: clang/test/CodeGen/builtins-arm.c
===================================================================
--- clang/test/CodeGen/builtins-arm.c
+++ clang/test/CodeGen/builtins-arm.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <stdint.h>
Index: clang/test/CodeGen/builtins-arm-exclusive.c
===================================================================
--- clang/test/CodeGen/builtins-arm-exclusive.c
+++ clang/test/CodeGen/builtins-arm-exclusive.c
@@ -1,6 +1,5 @@
-// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
-// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64
-
+// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64
struct Simple {
char a, b;
Index: clang/test/CodeGen/attr-coldhot.c
===================================================================
--- clang/test/CodeGen/attr-coldhot.c
+++ clang/test/CodeGen/attr-coldhot.c
@@ -1,4 +1,5 @@
-// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s -check-prefixes=CHECK,O0
+// RUN: %clang_cc1 -emit-llvm %s -o - -O1 -disable-llvm-passes | FileCheck %s -check-prefixes=CHECK,O1
int test1() __attribute__((__cold__)) {
return 42;
@@ -8,4 +9,5 @@
// CHECK: ret
}
-// CHECK: attributes [[ATTR]] = { {{.*}}cold{{.*}}optsize{{.*}} }
+// O0: attributes [[ATTR]] = { {{.*}}cold{{.*}}optnone{{.*}} }
+// O1: attributes [[ATTR]] = { {{.*}}cold{{.*}}optsize{{.*}} }
Index: clang/test/CodeGen/arm64_vdupq_n_f64.c
===================================================================
--- clang/test/CodeGen/arm64_vdupq_n_f64.c
+++ clang/test/CodeGen/arm64_vdupq_n_f64.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm64_vcopy.c
===================================================================
--- clang/test/CodeGen/arm64_vcopy.c
+++ clang/test/CodeGen/arm64_vcopy.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s
// Test ARM64 SIMD copy vector element to vector element: vcopyq_lane*
Index: clang/test/CodeGen/arm64-lanes.c
===================================================================
--- clang/test/CodeGen/arm64-lanes.c
+++ clang/test/CodeGen/arm64-lanes.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE
+// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-neon-vget.c
===================================================================
--- clang/test/CodeGen/arm-neon-vget.c
+++ clang/test/CodeGen/arm-neon-vget.c
@@ -4,7 +4,7 @@
// RUN: -mfloat-abi soft \
// RUN: -target-feature +soft-float-abi \
// RUN: -ffreestanding \
-// RUN: -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-neon-vcvtX.c
===================================================================
--- clang/test/CodeGen/arm-neon-vcvtX.c
+++ clang/test/CodeGen/arm-neon-vcvtX.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-neon-numeric-maxmin.c
===================================================================
--- clang/test/CodeGen/arm-neon-numeric-maxmin.c
+++ clang/test/CodeGen/arm-neon-numeric-maxmin.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-neon-fma.c
===================================================================
--- clang/test/CodeGen/arm-neon-fma.c
+++ clang/test/CodeGen/arm-neon-fma.c
@@ -3,7 +3,7 @@
// RUN: -target-cpu cortex-a7 \
// RUN: -mfloat-abi hard \
// RUN: -ffreestanding \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-neon-directed-rounding.c
===================================================================
--- clang/test/CodeGen/arm-neon-directed-rounding.c
+++ clang/test/CodeGen/arm-neon-directed-rounding.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/arm-crc32.c
===================================================================
--- clang/test/CodeGen/arm-crc32.c
+++ clang/test/CodeGen/arm-crc32.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple armv8-none-linux-gnueabi \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
int crc32b(int a, char b)
{
Index: clang/test/CodeGen/address-safety-attr.cpp
===================================================================
--- clang/test/CodeGen/address-safety-attr.cpp
+++ clang/test/CodeGen/address-safety-attr.cpp
@@ -3,16 +3,16 @@
// RUN: echo "struct S { S(){} ~S(){} };" >> %t.extra-source.cpp
// RUN: echo "S glob_array[5];" >> %t.extra-source.cpp
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s
// RUN: echo "fun:*BlacklistedFunction*" > %t.func.blacklist
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s
// The blacklist file uses regexps, so escape backslashes, which are common in
// Windows paths.
// RUN: echo "src:%s" | sed -e 's/\\/\\\\/g' > %t.file.blacklist
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s
// The sanitize_address attribute should be attached to functions
// when AddressSanitizer is enabled, unless no_sanitize_address attribute
Index: clang/test/CodeGen/address-safety-attr-kasan.cpp
===================================================================
--- clang/test/CodeGen/address-safety-attr-kasan.cpp
+++ clang/test/CodeGen/address-safety-attr-kasan.cpp
@@ -1,9 +1,9 @@
// Make sure the sanitize_address attribute is emitted when using both ASan and KASan.
// Also document that __attribute__((no_sanitize_address)) doesn't disable KASan instrumentation.
-/// RUN: %clang_cc1 -triple i386-unknown-linux -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NOASAN %s
-/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-ASAN %s
-/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=kernel-address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-KASAN %s
+/// RUN: %clang_cc1 -triple i386-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NOASAN %s
+/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=address -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-ASAN %s
+/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=kernel-address -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-KASAN %s
int HasSanitizeAddress() {
return 1;
Index: clang/test/CodeGen/aarch64-poly64.c
===================================================================
--- clang/test/CodeGen/aarch64-poly64.c
+++ clang/test/CodeGen/aarch64-poly64.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \
+// RUN: -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \
// RUN: | FileCheck %s
// Test new aarch64 intrinsics with poly64
Index: clang/test/CodeGen/aarch64-neon-vget.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-vget.c
+++ clang/test/CodeGen/aarch64-neon-vget.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon \
-// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \
+// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
// RUN: | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/aarch64-neon-vget-hilo.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-vget-hilo.c
+++ clang/test/CodeGen/aarch64-neon-vget-hilo.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \
+// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
// RUN: | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-vcombine.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-vcombine.c
+++ clang/test/CodeGen/aarch64-neon-vcombine.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-tbl.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-tbl.c
+++ clang/test/CodeGen/aarch64-neon-tbl.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-shifts.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-shifts.c
+++ clang/test/CodeGen/aarch64-neon-shifts.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
+++ clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-scalar-copy.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-scalar-copy.c
+++ clang/test/CodeGen/aarch64-neon-scalar-copy.c
@@ -1,6 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
-
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/aarch64-neon-perm.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-perm.c
+++ clang/test/CodeGen/aarch64-neon-perm.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
#include <arm_neon.h>
Index: clang/test/CodeGen/aarch64-neon-misc.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-misc.c
+++ clang/test/CodeGen/aarch64-neon-misc.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \
+// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
// RUN: | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-ldst-one.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-ldst-one.c
+++ clang/test/CodeGen/aarch64-neon-ldst-one.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \
+// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
// RUN: | opt -S -mem2reg | FileCheck %s
#include <arm_neon.h>
Index: clang/test/CodeGen/aarch64-neon-intrinsics.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -fallow-half-arguments-and-returns -ffp-contract=fast -S -emit-llvm -o - %s \
+// RUN: -fallow-half-arguments-and-returns -ffp-contract=fast -S -disable-O0-optnone -emit-llvm -o - %s \
// RUN: | opt -S -mem2reg \
// RUN: | FileCheck %s
Index: clang/test/CodeGen/aarch64-neon-fma.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-fma.c
+++ clang/test/CodeGen/aarch64-neon-fma.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
+++ clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-across.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-across.c
+++ clang/test/CodeGen/aarch64-neon-across.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-3v.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-3v.c
+++ clang/test/CodeGen/aarch64-neon-3v.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/test/CodeGen/aarch64-neon-2velem.c
===================================================================
--- clang/test/CodeGen/aarch64-neon-2velem.c
+++ clang/test/CodeGen/aarch64-neon-2velem.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// Test new aarch64 intrinsics and types
Index: clang/lib/Frontend/CompilerInvocation.cpp
===================================================================
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -521,6 +521,7 @@
Opts.DisableLLVMPasses = Args.hasArg(OPT_disable_llvm_passes);
Opts.DisableLifetimeMarkers = Args.hasArg(OPT_disable_lifetimemarkers);
+ Opts.DisableO0ImplyOptNone = Args.hasArg(OPT_disable_O0_optnone);
Opts.DisableRedZone = Args.hasArg(OPT_disable_red_zone);
Opts.ForbidGuardVariables = Args.hasArg(OPT_fforbid_guard_variables);
Opts.UseRegisterSizedBitfieldAccess = Args.hasArg(
Index: clang/lib/CodeGen/CodeGenModule.cpp
===================================================================
--- clang/lib/CodeGen/CodeGenModule.cpp
+++ clang/lib/CodeGen/CodeGenModule.cpp
@@ -889,7 +889,20 @@
return;
}
- if (D->hasAttr<OptimizeNoneAttr>()) {
+ // Track whether we need to add the optnone LLVM attribute,
+ // starting with the default for this optimization level.
+ bool ShouldAddOptNone =
+ !CodeGenOpts.DisableO0ImplyOptNone && CodeGenOpts.OptimizationLevel == 0;
+ // We can't add optnone in the following cases, it won't pass the verifier
+ ShouldAddOptNone &= !D->hasAttr<MinSizeAttr>();
+ ShouldAddOptNone &= !F->hasFnAttribute(llvm::Attribute::AlwaysInline);
+ ShouldAddOptNone &= !D->hasAttr<AlwaysInlineAttr>();
+ if (ShouldAddOptNone) {
+ B.addAttribute(llvm::Attribute::OptimizeNone);
+ B.addAttribute(llvm::Attribute::NoInline);
+ }
+
+ if (ShouldAddOptNone || D->hasAttr<OptimizeNoneAttr>()) {
B.addAttribute(llvm::Attribute::OptimizeNone);
// OptimizeNone implies noinline; we should not be inlining such functions.
@@ -902,7 +915,7 @@
if (D->hasAttr<NakedAttr>())
B.addAttribute(llvm::Attribute::Naked);
- // OptimizeNone wins over OptimizeForSize and MinSize.
+ // The OptimizeNone source attribute wins over OptimizeForSize and MinSize.
F->removeFnAttr(llvm::Attribute::OptimizeForSize);
F->removeFnAttr(llvm::Attribute::MinSize);
} else if (D->hasAttr<NakedAttr>()) {
@@ -943,7 +956,8 @@
// function.
if (!D->hasAttr<OptimizeNoneAttr>()) {
if (D->hasAttr<ColdAttr>()) {
- B.addAttribute(llvm::Attribute::OptimizeForSize);
+ if (!ShouldAddOptNone)
+ B.addAttribute(llvm::Attribute::OptimizeForSize);
B.addAttribute(llvm::Attribute::Cold);
}
Index: clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
===================================================================
--- clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
+++ clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
@@ -361,6 +361,7 @@
D, ThreadIDVar, InnermostKind, CodeGen);
OutlinedFun = cast<llvm::Function>(OutlinedFunVal);
OutlinedFun->removeFnAttr(llvm::Attribute::NoInline);
+ OutlinedFun->removeFnAttr(llvm::Attribute::OptimizeNone);
OutlinedFun->addFnAttr(llvm::Attribute::AlwaysInline);
} else
llvm_unreachable("parallel directive is not yet supported for nvptx "
Index: clang/lib/CodeGen/CGOpenMPRuntime.cpp
===================================================================
--- clang/lib/CodeGen/CGOpenMPRuntime.cpp
+++ clang/lib/CodeGen/CGOpenMPRuntime.cpp
@@ -758,6 +758,7 @@
IsCombiner ? ".omp_combiner." : ".omp_initializer.", &CGM.getModule());
CGM.SetInternalFunctionAttributes(/*D=*/nullptr, Fn, FnInfo);
Fn->removeFnAttr(llvm::Attribute::NoInline);
+ Fn->removeFnAttr(llvm::Attribute::OptimizeNone);
Fn->addFnAttr(llvm::Attribute::AlwaysInline);
CodeGenFunction CGF(CGM);
// Map "T omp_in;" variable to "*omp_in_parm" value in all expressions.
@@ -3486,6 +3487,7 @@
CGM.SetInternalFunctionAttributes(/*D=*/nullptr, TaskPrivatesMap,
TaskPrivatesMapFnInfo);
TaskPrivatesMap->removeFnAttr(llvm::Attribute::NoInline);
+ TaskPrivatesMap->removeFnAttr(llvm::Attribute::OptimizeNone);
TaskPrivatesMap->addFnAttr(llvm::Attribute::AlwaysInline);
CodeGenFunction CGF(CGM);
CGF.disableDebugInfo();
Index: clang/include/clang/Frontend/CodeGenOptions.def
===================================================================
--- clang/include/clang/Frontend/CodeGenOptions.def
+++ clang/include/clang/Frontend/CodeGenOptions.def
@@ -53,6 +53,7 @@
///< the pristine IR generated by the
///< frontend.
CODEGENOPT(DisableLifetimeMarkers, 1, 0) ///< Don't emit any lifetime markers
+CODEGENOPT(DisableO0ImplyOptNone , 1, 0) ///< Don't annonate function with optnone at O0
CODEGENOPT(ExperimentalNewPassManager, 1, 0) ///< Enables the new, experimental
///< pass manager.
CODEGENOPT(DisableRedZone , 1, 0) ///< Set when -mno-red-zone is enabled.
Index: clang/include/clang/Driver/CC1Options.td
===================================================================
--- clang/include/clang/Driver/CC1Options.td
+++ clang/include/clang/Driver/CC1Options.td
@@ -170,6 +170,8 @@
def disable_lifetimemarkers : Flag<["-"], "disable-lifetime-markers">,
HelpText<"Disable lifetime-markers emission even when optimizations are "
"enabled">;
+def disable_O0_optnone : Flag<["-"], "disable-O0-optnone">,
+ HelpText<"Disable adding the optnone attribute to functions at O0">;
def disable_red_zone : Flag<["-"], "disable-red-zone">,
HelpText<"Do not emit code that uses the red zone.">;
def dwarf_column_info : Flag<["-"], "dwarf-column-info">,
_______________________________________________
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