https://github.com/asi-sc updated https://github.com/llvm/llvm-project/pull/108406
>From 0c2925d18e8e4312a16d081c1c97d3298b85e8d4 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko <anton.sidore...@syntacore.com> Date: Mon, 2 Sep 2024 13:25:39 +0300 Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR7 processor definition Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core. The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march. Overview: https://syntacore.com/products/scr7 Scheduling model will be added in a subsequent PR. Co-authored-by: Dmitrii Petrov <dmitrii.pet...@syntacore.com> Co-authored-by: Anton Afanasyev <anton.afanas...@syntacore.com> Co-authored-by: Elena Lepilkina <elena.lepilk...@syntacore.com> --- clang/test/Driver/riscv-cpus.c | 25 +++++++++++++++++++ .../test/Misc/target-invalid-cpu-note/riscv.c | 2 ++ llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 19 ++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 481eaae9153e86..79256e402c0b74 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -502,3 +502,28 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s +// MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh" +// MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s +// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 96d3cefd434d78..7bbf3574af3c35 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -40,6 +40,7 @@ // RISCV64-SAME: {{^}}, syntacore-scr3-rv64 // RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 +// RISCV64-SAME: {{^}}, syntacore-scr7 // RISCV64-SAME: {{^}}, veyron-v1 // RISCV64-SAME: {{^}}, xiangshan-nanhu // RISCV64-SAME: {{$}} @@ -85,6 +86,7 @@ // TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 +// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7 // TUNE-RISCV64-SAME: {{^}}, veyron-v1 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu // TUNE-RISCV64-SAME: {{^}}, generic diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 52456896f2fc6c..6df4c37b092432 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -123,6 +123,7 @@ Changes to the RISC-V Backend largely untested. * The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally. * Added ``Smctr`` and ``Ssctr`` extensions. +* ``-mcpu=syntacore-scr7`` was added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index d4ec5ecc6489c1..c4e1a1457e8d30 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -383,6 +383,25 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", FeatureStdExtC], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtV, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZkn], + [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, [Feature64Bit, >From afc53347e8bcb030b5fe76eea77eef44c383f1dc Mon Sep 17 00:00:00 2001 From: Anton Sidorenko <anton.sidore...@syntacore.com> Date: Fri, 13 Sep 2024 11:49:15 +0300 Subject: [PATCH 2/2] fixup! [RISCV] Add Syntacore SCR7 processor definition --- clang/test/Driver/riscv-cpus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 79256e402c0b74..d36639d16ad4cb 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -510,6 +510,7 @@ // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f" // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d" // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+v" // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr" // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
