Author: Adam Yang Date: 2024-11-07T17:47:53-08:00 New Revision: 36d757f8406a00539228e15b44bb850936871421
URL: https://github.com/llvm/llvm-project/commit/36d757f8406a00539228e15b44bb850936871421 DIFF: https://github.com/llvm/llvm-project/commit/36d757f8406a00539228e15b44bb850936871421.diff LOG: [HLSL][SPIRV] Added clamp intrinsic (#113394) Fixes #88052 - Added the following intrinsics: - `int_spv_uclamp` - `int_spv_sclamp` - `int_spv_fclamp` - Updated DirectX counterparts to have the same three clamp intrinsics. - Update the clamp.hlsl unit tests to include SPIRV - Added the SPIRV specific tests Added: llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll llvm/test/CodeGen/SPIRV/opencl/clamp.ll Modified: clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CGHLSLRuntime.h clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl clang/test/CodeGenHLSL/builtins/clamp.hlsl llvm/include/llvm/IR/IntrinsicsDirectX.td llvm/include/llvm/IR/IntrinsicsSPIRV.td llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/test/CodeGen/DirectX/clamp.ll Removed: llvm/test/CodeGen/DirectX/clamp-vec.ll ################################################################################ diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 1b4891d94eee77..663e0882f7d0d7 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -18838,14 +18838,21 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Value *OpMax = EmitScalarExpr(E->getArg(2)); QualType Ty = E->getArg(0)->getType(); - bool IsUnsigned = false; if (auto *VecTy = Ty->getAs<VectorType>()) Ty = VecTy->getElementType(); - IsUnsigned = Ty->isUnsignedIntegerType(); + + Intrinsic::ID Intr; + if (Ty->isFloatingType()) { + Intr = CGM.getHLSLRuntime().getNClampIntrinsic(); + } else if (Ty->isUnsignedIntegerType()) { + Intr = CGM.getHLSLRuntime().getUClampIntrinsic(); + } else { + assert(Ty->isSignedIntegerType()); + Intr = CGM.getHLSLRuntime().getSClampIntrinsic(); + } return Builder.CreateIntrinsic( - /*ReturnType=*/OpX->getType(), - IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp, - ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp"); + /*ReturnType=*/OpX->getType(), Intr, + ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "hlsl.clamp"); } case Builtin::BI__builtin_hlsl_cross: { Value *Op0 = EmitScalarExpr(E->getArg(0)); diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index caf8777fd95a9f..94d0f85a50fa72 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -95,6 +95,9 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane) GENERATE_HLSL_INTRINSIC_FUNCTION(FirstBitUHigh, firstbituhigh) GENERATE_HLSL_INTRINSIC_FUNCTION(FirstBitSHigh, firstbitshigh) + GENERATE_HLSL_INTRINSIC_FUNCTION(NClamp, nclamp) + GENERATE_HLSL_INTRINSIC_FUNCTION(SClamp, sclamp) + GENERATE_HLSL_INTRINSIC_FUNCTION(UClamp, uclamp) GENERATE_HLSL_INTRINSIC_FUNCTION(CreateHandleFromBinding, handle_fromBinding) diff --git a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl index e3ef26429e7e40..62bada715a68ad 100644 --- a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl +++ b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm -disable-llvm-passes -o - | FileCheck %s // CHECK-LABEL: builtin_test_clamp_int4 -// CHECK: %dx.clamp = call <4 x i32> @llvm.dx.clamp.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) -// CHECK: ret <4 x i32> %dx.clamp +// CHECK: %hlsl.clamp = call <4 x i32> @llvm.dx.sclamp.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) +// CHECK: ret <4 x i32> %hlsl.clamp int4 builtin_test_clamp_int4(int4 p0, int4 p1, int4 p2) { return __builtin_hlsl_elementwise_clamp(p0, p1, p2); } diff --git a/clang/test/CodeGenHLSL/builtins/clamp.hlsl b/clang/test/CodeGenHLSL/builtins/clamp.hlsl index af8f6b9733a071..3489f3d3e2b09e 100644 --- a/clang/test/CodeGenHLSL/builtins/clamp.hlsl +++ b/clang/test/CodeGenHLSL/builtins/clamp.hlsl @@ -1,133 +1,143 @@ // RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \ // RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF +// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ +// RUN: -DTARGET=dx -DFNATTRS=noundef // RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \ // RUN: -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF +// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \ +// RUN: -DTARGET=dx -DFNATTRS=noundef +// RUN: %clang_cc1 -finclude-default-header -triple spirv-unknown-vulkan-compute %s \ +// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ +// RUN: -DTARGET=spv -DFNATTRS="spir_func noundef" +// RUN: %clang_cc1 -finclude-default-header -triple spirv-unknown-vulkan-compute %s \ +// RUN: -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \ +// RUN: -DTARGET=spv -DFNATTRS="spir_func noundef" #ifdef __HLSL_ENABLE_16_BIT -// NATIVE_HALF-LABEL: define noundef i16 @_Z16test_clamp_short -// NATIVE_HALF: call i16 @llvm.dx.clamp.i16( +// NATIVE_HALF: define [[FNATTRS]] i16 @_Z16test_clamp_short +// NATIVE_HALF: call i16 @llvm.[[TARGET]].sclamp.i16( int16_t test_clamp_short(int16_t p0, int16_t p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z17test_clamp_short2 -// NATIVE_HALF: call <2 x i16> @llvm.dx.clamp.v2i16( +// NATIVE_HALF: define [[FNATTRS]] <2 x i16> @_Z17test_clamp_short2 +// NATIVE_HALF: call <2 x i16> @llvm.[[TARGET]].sclamp.v2i16( int16_t2 test_clamp_short2(int16_t2 p0, int16_t2 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z17test_clamp_short3 -// NATIVE_HALF: call <3 x i16> @llvm.dx.clamp.v3i16 +// NATIVE_HALF: define [[FNATTRS]] <3 x i16> @_Z17test_clamp_short3 +// NATIVE_HALF: call <3 x i16> @llvm.[[TARGET]].sclamp.v3i16 int16_t3 test_clamp_short3(int16_t3 p0, int16_t3 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z17test_clamp_short4 -// NATIVE_HALF: call <4 x i16> @llvm.dx.clamp.v4i16 +// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z17test_clamp_short4 +// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].sclamp.v4i16 int16_t4 test_clamp_short4(int16_t4 p0, int16_t4 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef i16 @_Z17test_clamp_ushort -// NATIVE_HALF: call i16 @llvm.dx.uclamp.i16( +// NATIVE_HALF: define [[FNATTRS]] i16 @_Z17test_clamp_ushort +// NATIVE_HALF: call i16 @llvm.[[TARGET]].uclamp.i16( uint16_t test_clamp_ushort(uint16_t p0, uint16_t p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z18test_clamp_ushort2 -// NATIVE_HALF: call <2 x i16> @llvm.dx.uclamp.v2i16 +// NATIVE_HALF: define [[FNATTRS]] <2 x i16> @_Z18test_clamp_ushort2 +// NATIVE_HALF: call <2 x i16> @llvm.[[TARGET]].uclamp.v2i16 uint16_t2 test_clamp_ushort2(uint16_t2 p0, uint16_t2 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z18test_clamp_ushort3 -// NATIVE_HALF: call <3 x i16> @llvm.dx.uclamp.v3i16 +// NATIVE_HALF: define [[FNATTRS]] <3 x i16> @_Z18test_clamp_ushort3 +// NATIVE_HALF: call <3 x i16> @llvm.[[TARGET]].uclamp.v3i16 uint16_t3 test_clamp_ushort3(uint16_t3 p0, uint16_t3 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z18test_clamp_ushort4 -// NATIVE_HALF: call <4 x i16> @llvm.dx.uclamp.v4i16 +// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z18test_clamp_ushort4 +// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].uclamp.v4i16 uint16_t4 test_clamp_ushort4(uint16_t4 p0, uint16_t4 p1) { return clamp(p0, p1,p1); } #endif -// CHECK-LABEL: define noundef i32 @_Z14test_clamp_int -// CHECK: call i32 @llvm.dx.clamp.i32( +// CHECK: define [[FNATTRS]] i32 @_Z14test_clamp_int +// CHECK: call i32 @llvm.[[TARGET]].sclamp.i32( int test_clamp_int(int p0, int p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x i32> @_Z15test_clamp_int2 -// CHECK: call <2 x i32> @llvm.dx.clamp.v2i32 +// CHECK: define [[FNATTRS]] <2 x i32> @_Z15test_clamp_int2 +// CHECK: call <2 x i32> @llvm.[[TARGET]].sclamp.v2i32 int2 test_clamp_int2(int2 p0, int2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x i32> @_Z15test_clamp_int3 -// CHECK: call <3 x i32> @llvm.dx.clamp.v3i32 +// CHECK: define [[FNATTRS]] <3 x i32> @_Z15test_clamp_int3 +// CHECK: call <3 x i32> @llvm.[[TARGET]].sclamp.v3i32 int3 test_clamp_int3(int3 p0, int3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x i32> @_Z15test_clamp_int4 -// CHECK: call <4 x i32> @llvm.dx.clamp.v4i32 +// CHECK: define [[FNATTRS]] <4 x i32> @_Z15test_clamp_int4 +// CHECK: call <4 x i32> @llvm.[[TARGET]].sclamp.v4i32 int4 test_clamp_int4(int4 p0, int4 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef i32 @_Z15test_clamp_uint -// CHECK: call i32 @llvm.dx.uclamp.i32( +// CHECK: define [[FNATTRS]] i32 @_Z15test_clamp_uint +// CHECK: call i32 @llvm.[[TARGET]].uclamp.i32( int test_clamp_uint(uint p0, uint p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x i32> @_Z16test_clamp_uint2 -// CHECK: call <2 x i32> @llvm.dx.uclamp.v2i32 +// CHECK: define [[FNATTRS]] <2 x i32> @_Z16test_clamp_uint2 +// CHECK: call <2 x i32> @llvm.[[TARGET]].uclamp.v2i32 uint2 test_clamp_uint2(uint2 p0, uint2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x i32> @_Z16test_clamp_uint3 -// CHECK: call <3 x i32> @llvm.dx.uclamp.v3i32 +// CHECK: define [[FNATTRS]] <3 x i32> @_Z16test_clamp_uint3 +// CHECK: call <3 x i32> @llvm.[[TARGET]].uclamp.v3i32 uint3 test_clamp_uint3(uint3 p0, uint3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x i32> @_Z16test_clamp_uint4 -// CHECK: call <4 x i32> @llvm.dx.uclamp.v4i32 +// CHECK: define [[FNATTRS]] <4 x i32> @_Z16test_clamp_uint4 +// CHECK: call <4 x i32> @llvm.[[TARGET]].uclamp.v4i32 uint4 test_clamp_uint4(uint4 p0, uint4 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef i64 @_Z15test_clamp_long -// CHECK: call i64 @llvm.dx.clamp.i64( +// CHECK: define [[FNATTRS]] i64 @_Z15test_clamp_long +// CHECK: call i64 @llvm.[[TARGET]].sclamp.i64( int64_t test_clamp_long(int64_t p0, int64_t p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x i64> @_Z16test_clamp_long2 -// CHECK: call <2 x i64> @llvm.dx.clamp.v2i64 +// CHECK: define [[FNATTRS]] <2 x i64> @_Z16test_clamp_long2 +// CHECK: call <2 x i64> @llvm.[[TARGET]].sclamp.v2i64 int64_t2 test_clamp_long2(int64_t2 p0, int64_t2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x i64> @_Z16test_clamp_long3 -// CHECK: call <3 x i64> @llvm.dx.clamp.v3i64 +// CHECK: define [[FNATTRS]] <3 x i64> @_Z16test_clamp_long3 +// CHECK: call <3 x i64> @llvm.[[TARGET]].sclamp.v3i64 int64_t3 test_clamp_long3(int64_t3 p0, int64_t3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x i64> @_Z16test_clamp_long4 -// CHECK: call <4 x i64> @llvm.dx.clamp.v4i64 +// CHECK: define [[FNATTRS]] <4 x i64> @_Z16test_clamp_long4 +// CHECK: call <4 x i64> @llvm.[[TARGET]].sclamp.v4i64 int64_t4 test_clamp_long4(int64_t4 p0, int64_t4 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef i64 @_Z16test_clamp_ulong -// CHECK: call i64 @llvm.dx.uclamp.i64( +// CHECK: define [[FNATTRS]] i64 @_Z16test_clamp_ulong +// CHECK: call i64 @llvm.[[TARGET]].uclamp.i64( uint64_t test_clamp_ulong(uint64_t p0, uint64_t p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x i64> @_Z17test_clamp_ulong2 -// CHECK: call <2 x i64> @llvm.dx.uclamp.v2i64 +// CHECK: define [[FNATTRS]] <2 x i64> @_Z17test_clamp_ulong2 +// CHECK: call <2 x i64> @llvm.[[TARGET]].uclamp.v2i64 uint64_t2 test_clamp_ulong2(uint64_t2 p0, uint64_t2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x i64> @_Z17test_clamp_ulong3 -// CHECK: call <3 x i64> @llvm.dx.uclamp.v3i64 +// CHECK: define [[FNATTRS]] <3 x i64> @_Z17test_clamp_ulong3 +// CHECK: call <3 x i64> @llvm.[[TARGET]].uclamp.v3i64 uint64_t3 test_clamp_ulong3(uint64_t3 p0, uint64_t3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x i64> @_Z17test_clamp_ulong4 -// CHECK: call <4 x i64> @llvm.dx.uclamp.v4i64 +// CHECK: define [[FNATTRS]] <4 x i64> @_Z17test_clamp_ulong4 +// CHECK: call <4 x i64> @llvm.[[TARGET]].uclamp.v4i64 uint64_t4 test_clamp_ulong4(uint64_t4 p0, uint64_t4 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef half @_Z15test_clamp_half -// NATIVE_HALF: call half @llvm.dx.clamp.f16( -// NO_HALF-LABEL: define noundef float @_Z15test_clamp_half -// NO_HALF: call float @llvm.dx.clamp.f32( +// NATIVE_HALF: define [[FNATTRS]] half @_Z15test_clamp_half +// NATIVE_HALF: call half @llvm.[[TARGET]].nclamp.f16( +// NO_HALF: define [[FNATTRS]] float @_Z15test_clamp_half +// NO_HALF: call float @llvm.[[TARGET]].nclamp.f32( half test_clamp_half(half p0, half p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <2 x half> @_Z16test_clamp_half2 -// NATIVE_HALF: call <2 x half> @llvm.dx.clamp.v2f16 -// NO_HALF-LABEL: define noundef <2 x float> @_Z16test_clamp_half2 -// NO_HALF: call <2 x float> @llvm.dx.clamp.v2f32( +// NATIVE_HALF: define [[FNATTRS]] <2 x half> @_Z16test_clamp_half2 +// NATIVE_HALF: call <2 x half> @llvm.[[TARGET]].nclamp.v2f16 +// NO_HALF: define [[FNATTRS]] <2 x float> @_Z16test_clamp_half2 +// NO_HALF: call <2 x float> @llvm.[[TARGET]].nclamp.v2f32( half2 test_clamp_half2(half2 p0, half2 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <3 x half> @_Z16test_clamp_half3 -// NATIVE_HALF: call <3 x half> @llvm.dx.clamp.v3f16 -// NO_HALF-LABEL: define noundef <3 x float> @_Z16test_clamp_half3 -// NO_HALF: call <3 x float> @llvm.dx.clamp.v3f32( +// NATIVE_HALF: define [[FNATTRS]] <3 x half> @_Z16test_clamp_half3 +// NATIVE_HALF: call <3 x half> @llvm.[[TARGET]].nclamp.v3f16 +// NO_HALF: define [[FNATTRS]] <3 x float> @_Z16test_clamp_half3 +// NO_HALF: call <3 x float> @llvm.[[TARGET]].nclamp.v3f32( half3 test_clamp_half3(half3 p0, half3 p1) { return clamp(p0, p1,p1); } -// NATIVE_HALF-LABEL: define noundef <4 x half> @_Z16test_clamp_half4 -// NATIVE_HALF: call <4 x half> @llvm.dx.clamp.v4f16 -// NO_HALF-LABEL: define noundef <4 x float> @_Z16test_clamp_half4 -// NO_HALF: call <4 x float> @llvm.dx.clamp.v4f32( +// NATIVE_HALF: define [[FNATTRS]] <4 x half> @_Z16test_clamp_half4 +// NATIVE_HALF: call <4 x half> @llvm.[[TARGET]].nclamp.v4f16 +// NO_HALF: define [[FNATTRS]] <4 x float> @_Z16test_clamp_half4 +// NO_HALF: call <4 x float> @llvm.[[TARGET]].nclamp.v4f32( half4 test_clamp_half4(half4 p0, half4 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef float @_Z16test_clamp_float -// CHECK: call float @llvm.dx.clamp.f32( +// CHECK: define [[FNATTRS]] float @_Z16test_clamp_float +// CHECK: call float @llvm.[[TARGET]].nclamp.f32( float test_clamp_float(float p0, float p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x float> @_Z17test_clamp_float2 -// CHECK: call <2 x float> @llvm.dx.clamp.v2f32 +// CHECK: define [[FNATTRS]] <2 x float> @_Z17test_clamp_float2 +// CHECK: call <2 x float> @llvm.[[TARGET]].nclamp.v2f32 float2 test_clamp_float2(float2 p0, float2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x float> @_Z17test_clamp_float3 -// CHECK: call <3 x float> @llvm.dx.clamp.v3f32 +// CHECK: define [[FNATTRS]] <3 x float> @_Z17test_clamp_float3 +// CHECK: call <3 x float> @llvm.[[TARGET]].nclamp.v3f32 float3 test_clamp_float3(float3 p0, float3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x float> @_Z17test_clamp_float4 -// CHECK: call <4 x float> @llvm.dx.clamp.v4f32 +// CHECK: define [[FNATTRS]] <4 x float> @_Z17test_clamp_float4 +// CHECK: call <4 x float> @llvm.[[TARGET]].nclamp.v4f32 float4 test_clamp_float4(float4 p0, float4 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef double @_Z17test_clamp_double -// CHECK: call double @llvm.dx.clamp.f64( +// CHECK: define [[FNATTRS]] double @_Z17test_clamp_double +// CHECK: call double @llvm.[[TARGET]].nclamp.f64( double test_clamp_double(double p0, double p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <2 x double> @_Z18test_clamp_double2 -// CHECK: call <2 x double> @llvm.dx.clamp.v2f64 +// CHECK: define [[FNATTRS]] <2 x double> @_Z18test_clamp_double2 +// CHECK: call <2 x double> @llvm.[[TARGET]].nclamp.v2f64 double2 test_clamp_double2(double2 p0, double2 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <3 x double> @_Z18test_clamp_double3 -// CHECK: call <3 x double> @llvm.dx.clamp.v3f64 +// CHECK: define [[FNATTRS]] <3 x double> @_Z18test_clamp_double3 +// CHECK: call <3 x double> @llvm.[[TARGET]].nclamp.v3f64 double3 test_clamp_double3(double3 p0, double3 p1) { return clamp(p0, p1,p1); } -// CHECK-LABEL: define noundef <4 x double> @_Z18test_clamp_double4 -// CHECK: call <4 x double> @llvm.dx.clamp.v4f64 +// CHECK: define [[FNATTRS]] <4 x double> @_Z18test_clamp_double4 +// CHECK: call <4 x double> @llvm.[[TARGET]].nclamp.v4f64 double4 test_clamp_double4(double4 p0, double4 p1) { return clamp(p0, p1,p1); } diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index c181424a6e95bf..da42909eedf787 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -43,8 +43,9 @@ def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>; def int_dx_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; def int_dx_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; -def int_dx_clamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; def int_dx_uclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; +def int_dx_sclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; +def int_dx_nclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; def int_dx_cross : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; def int_dx_saturate : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index e93d6fa83de61b..798a9e795a16f0 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -90,6 +90,9 @@ let TargetPrefix = "spv" in { def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int_spv_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>; + def int_spv_uclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + def int_spv_nclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; // Create resource handle given the binding information. Returns a // type appropriate for the kind of resource given the set id, binding id, diff --git a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp index fb5383b3514a5a..d2bfca1fada559 100644 --- a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp +++ b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp @@ -53,9 +53,10 @@ static bool isIntrinsicExpansion(Function &F) { case Intrinsic::pow: case Intrinsic::dx_all: case Intrinsic::dx_any: - case Intrinsic::dx_clamp: case Intrinsic::dx_cross: case Intrinsic::dx_uclamp: + case Intrinsic::dx_sclamp: + case Intrinsic::dx_nclamp: case Intrinsic::dx_degrees: case Intrinsic::dx_lerp: case Intrinsic::dx_length: @@ -452,29 +453,21 @@ static Value *expandRadiansIntrinsic(CallInst *Orig) { return Builder.CreateFMul(X, PiOver180); } -static Intrinsic::ID getMaxForClamp(Type *ElemTy, - Intrinsic::ID ClampIntrinsic) { +static Intrinsic::ID getMaxForClamp(Intrinsic::ID ClampIntrinsic) { if (ClampIntrinsic == Intrinsic::dx_uclamp) return Intrinsic::umax; - assert(ClampIntrinsic == Intrinsic::dx_clamp); - if (ElemTy->isVectorTy()) - ElemTy = ElemTy->getScalarType(); - if (ElemTy->isIntegerTy()) + if (ClampIntrinsic == Intrinsic::dx_sclamp) return Intrinsic::smax; - assert(ElemTy->isFloatingPointTy()); + assert(ClampIntrinsic == Intrinsic::dx_nclamp); return Intrinsic::maxnum; } -static Intrinsic::ID getMinForClamp(Type *ElemTy, - Intrinsic::ID ClampIntrinsic) { +static Intrinsic::ID getMinForClamp(Intrinsic::ID ClampIntrinsic) { if (ClampIntrinsic == Intrinsic::dx_uclamp) return Intrinsic::umin; - assert(ClampIntrinsic == Intrinsic::dx_clamp); - if (ElemTy->isVectorTy()) - ElemTy = ElemTy->getScalarType(); - if (ElemTy->isIntegerTy()) + if (ClampIntrinsic == Intrinsic::dx_sclamp) return Intrinsic::smin; - assert(ElemTy->isFloatingPointTy()); + assert(ClampIntrinsic == Intrinsic::dx_nclamp); return Intrinsic::minnum; } @@ -485,9 +478,9 @@ static Value *expandClampIntrinsic(CallInst *Orig, Value *Max = Orig->getOperand(2); Type *Ty = X->getType(); IRBuilder<> Builder(Orig); - auto *MaxCall = Builder.CreateIntrinsic( - Ty, getMaxForClamp(Ty, ClampIntrinsic), {X, Min}, nullptr, "dx.max"); - return Builder.CreateIntrinsic(Ty, getMinForClamp(Ty, ClampIntrinsic), + auto *MaxCall = Builder.CreateIntrinsic(Ty, getMaxForClamp(ClampIntrinsic), + {X, Min}, nullptr, "dx.max"); + return Builder.CreateIntrinsic(Ty, getMinForClamp(ClampIntrinsic), {MaxCall, Max}, nullptr, "dx.min"); } @@ -555,7 +548,8 @@ static bool expandIntrinsic(Function &F, CallInst *Orig) { Result = expandCrossIntrinsic(Orig); break; case Intrinsic::dx_uclamp: - case Intrinsic::dx_clamp: + case Intrinsic::dx_sclamp: + case Intrinsic::dx_nclamp: Result = expandClampIntrinsic(Orig, IntrinsicId); break; case Intrinsic::dx_degrees: diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 414583aea91e64..cba681d7af2730 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2739,6 +2739,12 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, } break; case Intrinsic::spv_saturate: return selectSaturate(ResVReg, ResType, I); + case Intrinsic::spv_nclamp: + return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp); + case Intrinsic::spv_uclamp: + return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp); + case Intrinsic::spv_sclamp: + return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp); case Intrinsic::spv_wave_is_first_lane: { SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); return BuildMI(BB, I, I.getDebugLoc(), diff --git a/llvm/test/CodeGen/DirectX/clamp-vec.ll b/llvm/test/CodeGen/DirectX/clamp-vec.ll deleted file mode 100644 index d4f33a18b71573..00000000000000 --- a/llvm/test/CodeGen/DirectX/clamp-vec.ll +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: opt -S -dxil-intrinsic-expansion < %s | FileCheck %s - -; Make sure dxil operation function calls for clamp are generated for float/int/uint vectors. - -; CHECK-LABEL: clamp_half3 -define noundef <3 x half> @clamp_half3(<3 x half> noundef %a, <3 x half> noundef %b, <3 x half> noundef %c) { -entry: - ; CHECK: call <3 x half> @llvm.maxnum.v3f16(<3 x half> %a, <3 x half> %b) - ; CHECK: call <3 x half> @llvm.minnum.v3f16(<3 x half> %{{.*}}, <3 x half> %c) - %dx.clamp = call <3 x half> @llvm.dx.clamp.v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c) - ret <3 x half> %dx.clamp -} - -; CHECK-LABEL: clamp_float4 -define noundef <4 x float> @clamp_float4(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) { -entry: - ; CHECK: call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) - ; CHECK: call <4 x float> @llvm.minnum.v4f32(<4 x float> %{{.*}}, <4 x float> %c) - %dx.clamp = call <4 x float> @llvm.dx.clamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) - ret <4 x float> %dx.clamp -} - -; CHECK-LABEL: clamp_double2 -define noundef <2 x double> @clamp_double2(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) { -entry: - ; CHECK: call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b) - ; CHECK: call <2 x double> @llvm.minnum.v2f64(<2 x double> %{{.*}}, <2 x double> %c) - %dx.clamp = call <2 x double> @llvm.dx.clamp.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) - ret <2 x double> %dx.clamp -} - -; CHECK-LABEL: clamp_int4 -define noundef <4 x i32> @clamp_int4(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { -entry: - ; CHECK: call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b) - ; CHECK: call <4 x i32> @llvm.smin.v4i32(<4 x i32> %{{.*}}, <4 x i32> %c) - %dx.clamp = call <4 x i32> @llvm.dx.clamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) - ret <4 x i32> %dx.clamp -} - -; CHECK-LABEL: clamp_uint16_t3 -define noundef <3 x i16> @clamp_uint16_t3(<3 x i16> noundef %a, <3 x i16> noundef %b, <3 x i16> noundef %c) { -entry: - ; CHECK: call <3 x i16> @llvm.umax.v3i16(<3 x i16> %a, <3 x i16> %b) - ; CHECK: call <3 x i16> @llvm.umin.v3i16(<3 x i16> %{{.*}}, <3 x i16> %c) - %dx.clamp = call <3 x i16> @llvm.dx.uclamp.v3i16(<3 x i16> %a, <3 x i16> %b, <3 x i16> %c) - ret <3 x i16> %dx.clamp -} - -; CHECK-LABEL: clamp_uint4 -define noundef <4 x i32> @clamp_uint4(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { -entry: - ; CHECK: call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b) - ; CHECK: call <4 x i32> @llvm.umin.v4i32(<4 x i32> %{{.*}}, <4 x i32> %c) - %dx.clamp = call <4 x i32> @llvm.dx.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) - ret <4 x i32> %dx.clamp -} - -; CHECK-LABEL: clamp_uint64_t4 -define noundef <2 x i64> @clamp_uint64_t4(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) { -entry: - ; CHECK: call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b) - ; CHECK: call <2 x i64> @llvm.umin.v2i64(<2 x i64> %{{.*}}, <2 x i64> %c) - %dx.clamp = call <2 x i64> @llvm.dx.uclamp.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) - ret <2 x i64> %dx.clamp -} - -declare <3 x half> @llvm.dx.clamp.v3f16(<3 x half>, <3 x half>, <3 x half>) -declare <4 x float> @llvm.dx.clamp.v4f32(<4 x float>, <4 x float>, <4 x float>) -declare <2 x double> @llvm.dx.clamp.v2f64(<2 x double>, <2 x double>, <2 x double>) -declare <4 x i32> @llvm.dx.clamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) -declare <3 x i16> @llvm.dx.uclamp.v3i32(<3 x i16>, <3 x i32>, <3 x i16>) -declare <4 x i32> @llvm.dx.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) -declare <2 x i64> @llvm.dx.uclamp.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) diff --git a/llvm/test/CodeGen/DirectX/clamp.ll b/llvm/test/CodeGen/DirectX/clamp.ll index 23aadf893e8ca7..6345abc1789bcf 100644 --- a/llvm/test/CodeGen/DirectX/clamp.ll +++ b/llvm/test/CodeGen/DirectX/clamp.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -dxil-intrinsic-expansion -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s +; RUN: opt -S -dxil-intrinsic-expansion -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s ; Make sure dxil operation function calls for clamp/uclamp are generated for half/float/double/i16/i32/i64. @@ -7,7 +7,7 @@ define noundef i16 @test_clamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef % entry: ; CHECK: call i16 @dx.op.binary.i16(i32 37, i16 %{{.*}}, i16 %{{.*}}) ; CHECK: call i16 @dx.op.binary.i16(i32 38, i16 %{{.*}}, i16 %{{.*}}) - %0 = call i16 @llvm.dx.clamp.i16(i16 %a, i16 %b, i16 %c) + %0 = call i16 @llvm.dx.sclamp.i16(i16 %a, i16 %b, i16 %c) ret i16 %0 } @@ -16,7 +16,7 @@ define noundef i32 @test_clamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef % entry: ; CHECK: call i32 @dx.op.binary.i32(i32 37, i32 %{{.*}}, i32 %{{.*}}) ; CHECK: call i32 @dx.op.binary.i32(i32 38, i32 %{{.*}}, i32 %{{.*}}) - %0 = call i32 @llvm.dx.clamp.i32(i32 %a, i32 %b, i32 %c) + %0 = call i32 @llvm.dx.sclamp.i32(i32 %a, i32 %b, i32 %c) ret i32 %0 } @@ -25,7 +25,7 @@ define noundef i64 @test_clamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef % entry: ; CHECK: call i64 @dx.op.binary.i64(i32 37, i64 %a, i64 %b) ; CHECK: call i64 @dx.op.binary.i64(i32 38, i64 %{{.*}}, i64 %c) - %0 = call i64 @llvm.dx.clamp.i64(i64 %a, i64 %b, i64 %c) + %0 = call i64 @llvm.dx.sclamp.i64(i64 %a, i64 %b, i64 %c) ret i64 %0 } @@ -34,7 +34,7 @@ define noundef half @test_clamp_half(half noundef %a, half noundef %b, half noun entry: ; CHECK: call half @dx.op.binary.f16(i32 35, half %{{.*}}, half %{{.*}}) ; CHECK: call half @dx.op.binary.f16(i32 36, half %{{.*}}, half %{{.*}}) - %0 = call half @llvm.dx.clamp.f16(half %a, half %b, half %c) + %0 = call half @llvm.dx.nclamp.f16(half %a, half %b, half %c) ret half %0 } @@ -43,7 +43,7 @@ define noundef float @test_clamp_float(float noundef %a, float noundef %b, float entry: ; CHECK: call float @dx.op.binary.f32(i32 35, float %{{.*}}, float %{{.*}}) ; CHECK: call float @dx.op.binary.f32(i32 36, float %{{.*}}, float %{{.*}}) - %0 = call float @llvm.dx.clamp.f32(float %a, float %b, float %c) + %0 = call float @llvm.dx.nclamp.f32(float %a, float %b, float %c) ret float %0 } @@ -52,7 +52,7 @@ define noundef double @test_clamp_double(double noundef %a, double noundef %b, d entry: ; CHECK: call double @dx.op.binary.f64(i32 35, double %{{.*}}, double %{{.*}}) ; CHECK: call double @dx.op.binary.f64(i32 36, double %{{.*}}, double %{{.*}}) - %0 = call double @llvm.dx.clamp.f64(double %a, double %b, double %c) + %0 = call double @llvm.dx.nclamp.f64(double %a, double %b, double %c) ret double %0 } @@ -83,12 +83,210 @@ entry: ret i64 %0 } -declare half @llvm.dx.clamp.f16(half, half, half) -declare float @llvm.dx.clamp.f32(float, float, float) -declare double @llvm.dx.clamp.f64(double, double, double) -declare i16 @llvm.dx.clamp.i16(i16, i16, i16) -declare i32 @llvm.dx.clamp.i32(i32, i32, i32) -declare i64 @llvm.dx.clamp.i64(i64, i64, i64) +declare half @llvm.dx.nclamp.f16(half, half, half) +declare float @llvm.dx.nclamp.f32(float, float, float) +declare double @llvm.dx.nclamp.f64(double, double, double) +declare i16 @llvm.dx.sclamp.i16(i16, i16, i16) +declare i32 @llvm.dx.sclamp.i32(i32, i32, i32) +declare i64 @llvm.dx.sclamp.i64(i64, i64, i64) declare i16 @llvm.dx.uclamp.i16(i16, i16, i16) declare i32 @llvm.dx.uclamp.i32(i32, i32, i32) declare i64 @llvm.dx.uclamp.i64(i64, i64, i64) + +; CHECK-LABEL: clamp_half3 +define noundef <3 x half> @clamp_half3(<3 x half> noundef %a, <3 x half> noundef %b, <3 x half> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <3 x half> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <3 x half> %a, i64 1 + ; CHECK-DAG: %[[a2:.+]] = extractelement <3 x half> %a, i64 2 + ; CHECK-DAG: %[[b0:.+]] = extractelement <3 x half> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <3 x half> %b, i64 1 + ; CHECK-DAG: %[[b2:.+]] = extractelement <3 x half> %b, i64 2 + ; CHECK-DAG: %[[c0:.+]] = extractelement <3 x half> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <3 x half> %c, i64 1 + ; CHECK-DAG: %[[c2:.+]] = extractelement <3 x half> %c, i64 2 + ; CHECK-DAG: %[[max0:.+]] = call half @dx.op.binary.f16(i32 35, half %[[a0]], half %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call half @dx.op.binary.f16(i32 35, half %[[a1]], half %[[b1]]) + ; CHECK-DAG: %[[max2:.+]] = call half @dx.op.binary.f16(i32 35, half %[[a2]], half %[[b2]]) + ; CHECK-DAG: %[[min0:.+]] = call half @dx.op.binary.f16(i32 36, half %[[max0]], half %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call half @dx.op.binary.f16(i32 36, half %[[max1]], half %[[c1]]) + ; CHECK-DAG: %[[min2:.+]] = call half @dx.op.binary.f16(i32 36, half %[[max2]], half %[[c2]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <3 x half> poison, half %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <3 x half> %[[ret0]], half %[[min1]], i64 1 + ; CHECK-DAG: %[[ret2:.+]] = insertelement <3 x half> %[[ret1]], half %[[min2]], i64 2 + ; CHECK: ret <3 x half> %[[ret2]] + %dx.clamp = call <3 x half> @llvm.dx.nclamp.v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c) + ret <3 x half> %dx.clamp +} + +; CHECK-LABEL: clamp_float4 +define noundef <4 x float> @clamp_float4(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <4 x float> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <4 x float> %a, i64 1 + ; CHECK-DAG: %[[a2:.+]] = extractelement <4 x float> %a, i64 2 + ; CHECK-DAG: %[[a3:.+]] = extractelement <4 x float> %a, i64 3 + ; CHECK-DAG: %[[b0:.+]] = extractelement <4 x float> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <4 x float> %b, i64 1 + ; CHECK-DAG: %[[b2:.+]] = extractelement <4 x float> %b, i64 2 + ; CHECK-DAG: %[[b3:.+]] = extractelement <4 x float> %b, i64 3 + ; CHECK-DAG: %[[c0:.+]] = extractelement <4 x float> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <4 x float> %c, i64 1 + ; CHECK-DAG: %[[c2:.+]] = extractelement <4 x float> %c, i64 2 + ; CHECK-DAG: %[[c3:.+]] = extractelement <4 x float> %c, i64 3 + ; CHECK-DAG: %[[max0:.+]] = call float @dx.op.binary.f32(i32 35, float %[[a0]], float %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call float @dx.op.binary.f32(i32 35, float %[[a1]], float %[[b1]]) + ; CHECK-DAG: %[[max2:.+]] = call float @dx.op.binary.f32(i32 35, float %[[a2]], float %[[b2]]) + ; CHECK-DAG: %[[max3:.+]] = call float @dx.op.binary.f32(i32 35, float %[[a3]], float %[[b3]]) + ; CHECK-DAG: %[[min0:.+]] = call float @dx.op.binary.f32(i32 36, float %[[max0]], float %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call float @dx.op.binary.f32(i32 36, float %[[max1]], float %[[c1]]) + ; CHECK-DAG: %[[min2:.+]] = call float @dx.op.binary.f32(i32 36, float %[[max2]], float %[[c2]]) + ; CHECK-DAG: %[[min3:.+]] = call float @dx.op.binary.f32(i32 36, float %[[max3]], float %[[c3]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <4 x float> poison, float %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <4 x float> %[[ret0]], float %[[min1]], i64 1 + ; CHECK-DAG: %[[ret2:.+]] = insertelement <4 x float> %[[ret1]], float %[[min2]], i64 2 + ; CHECK-DAG: %[[ret3:.+]] = insertelement <4 x float> %[[ret2]], float %[[min3]], i64 3 + ; CHECK: ret <4 x float> %[[ret3]] + %dx.clamp = call <4 x float> @llvm.dx.nclamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) + ret <4 x float> %dx.clamp +} + +; CHECK-LABEL: clamp_double2 +define noundef <2 x double> @clamp_double2(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <2 x double> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <2 x double> %a, i64 1 + ; CHECK-DAG: %[[b0:.+]] = extractelement <2 x double> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <2 x double> %b, i64 1 + ; CHECK-DAG: %[[c0:.+]] = extractelement <2 x double> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <2 x double> %c, i64 1 + ; CHECK-DAG: %[[max0:.+]] = call double @dx.op.binary.f64(i32 35, double %[[a0]], double %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call double @dx.op.binary.f64(i32 35, double %[[a1]], double %[[b1]]) + ; CHECK-DAG: %[[min0:.+]] = call double @dx.op.binary.f64(i32 36, double %[[max0]], double %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call double @dx.op.binary.f64(i32 36, double %[[max1]], double %[[c1]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <2 x double> poison, double %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <2 x double> %[[ret0]], double %[[min1]], i64 1 + ; CHECK: ret <2 x double> %[[ret1]] + %dx.clamp = call <2 x double> @llvm.dx.nclamp.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) + ret <2 x double> %dx.clamp +} + +; CHECK-LABEL: clamp_int4 +define noundef <4 x i32> @clamp_int4(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <4 x i32> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <4 x i32> %a, i64 1 + ; CHECK-DAG: %[[a2:.+]] = extractelement <4 x i32> %a, i64 2 + ; CHECK-DAG: %[[a3:.+]] = extractelement <4 x i32> %a, i64 3 + ; CHECK-DAG: %[[b0:.+]] = extractelement <4 x i32> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <4 x i32> %b, i64 1 + ; CHECK-DAG: %[[b2:.+]] = extractelement <4 x i32> %b, i64 2 + ; CHECK-DAG: %[[b3:.+]] = extractelement <4 x i32> %b, i64 3 + ; CHECK-DAG: %[[c0:.+]] = extractelement <4 x i32> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <4 x i32> %c, i64 1 + ; CHECK-DAG: %[[c2:.+]] = extractelement <4 x i32> %c, i64 2 + ; CHECK-DAG: %[[c3:.+]] = extractelement <4 x i32> %c, i64 3 + ; CHECK-DAG: %[[max0:.+]] = call i32 @dx.op.binary.i32(i32 37, i32 %[[a0]], i32 %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call i32 @dx.op.binary.i32(i32 37, i32 %[[a1]], i32 %[[b1]]) + ; CHECK-DAG: %[[max2:.+]] = call i32 @dx.op.binary.i32(i32 37, i32 %[[a2]], i32 %[[b2]]) + ; CHECK-DAG: %[[max3:.+]] = call i32 @dx.op.binary.i32(i32 37, i32 %[[a3]], i32 %[[b3]]) + ; CHECK-DAG: %[[min0:.+]] = call i32 @dx.op.binary.i32(i32 38, i32 %[[max0]], i32 %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call i32 @dx.op.binary.i32(i32 38, i32 %[[max1]], i32 %[[c1]]) + ; CHECK-DAG: %[[min2:.+]] = call i32 @dx.op.binary.i32(i32 38, i32 %[[max2]], i32 %[[c2]]) + ; CHECK-DAG: %[[min3:.+]] = call i32 @dx.op.binary.i32(i32 38, i32 %[[max3]], i32 %[[c3]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <4 x i32> poison, i32 %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <4 x i32> %[[ret0]], i32 %[[min1]], i64 1 + ; CHECK-DAG: %[[ret2:.+]] = insertelement <4 x i32> %[[ret1]], i32 %[[min2]], i64 2 + ; CHECK-DAG: %[[ret3:.+]] = insertelement <4 x i32> %[[ret2]], i32 %[[min3]], i64 3 + ; CHECK: ret <4 x i32> %[[ret3]] + %dx.clamp = call <4 x i32> @llvm.dx.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %dx.clamp +} + +; CHECK-LABEL: clamp_uint16_t3 +define noundef <3 x i16> @clamp_uint16_t3(<3 x i16> noundef %a, <3 x i16> noundef %b, <3 x i16> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <3 x i16> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <3 x i16> %a, i64 1 + ; CHECK-DAG: %[[a2:.+]] = extractelement <3 x i16> %a, i64 2 + ; CHECK-DAG: %[[b0:.+]] = extractelement <3 x i16> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <3 x i16> %b, i64 1 + ; CHECK-DAG: %[[b2:.+]] = extractelement <3 x i16> %b, i64 2 + ; CHECK-DAG: %[[c0:.+]] = extractelement <3 x i16> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <3 x i16> %c, i64 1 + ; CHECK-DAG: %[[c2:.+]] = extractelement <3 x i16> %c, i64 2 + ; CHECK-DAG: %[[max0:.+]] = call i16 @dx.op.binary.i16(i32 39, i16 %[[a0]], i16 %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call i16 @dx.op.binary.i16(i32 39, i16 %[[a1]], i16 %[[b1]]) + ; CHECK-DAG: %[[max2:.+]] = call i16 @dx.op.binary.i16(i32 39, i16 %[[a2]], i16 %[[b2]]) + ; CHECK-DAG: %[[min0:.+]] = call i16 @dx.op.binary.i16(i32 40, i16 %[[max0]], i16 %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call i16 @dx.op.binary.i16(i32 40, i16 %[[max1]], i16 %[[c1]]) + ; CHECK-DAG: %[[min2:.+]] = call i16 @dx.op.binary.i16(i32 40, i16 %[[max2]], i16 %[[c2]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <3 x i16> poison, i16 %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <3 x i16> %[[ret0]], i16 %[[min1]], i64 1 + ; CHECK-DAG: %[[ret2:.+]] = insertelement <3 x i16> %[[ret1]], i16 %[[min2]], i64 2 + ; CHECK: ret <3 x i16> %[[ret2]] + %dx.clamp = call <3 x i16> @llvm.dx.uclamp.v3i16(<3 x i16> %a, <3 x i16> %b, <3 x i16> %c) + ret <3 x i16> %dx.clamp +} + +; CHECK-LABEL: clamp_uint4 +define noundef <4 x i32> @clamp_uint4(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <4 x i32> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <4 x i32> %a, i64 1 + ; CHECK-DAG: %[[a2:.+]] = extractelement <4 x i32> %a, i64 2 + ; CHECK-DAG: %[[a3:.+]] = extractelement <4 x i32> %a, i64 3 + ; CHECK-DAG: %[[b0:.+]] = extractelement <4 x i32> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <4 x i32> %b, i64 1 + ; CHECK-DAG: %[[b2:.+]] = extractelement <4 x i32> %b, i64 2 + ; CHECK-DAG: %[[b3:.+]] = extractelement <4 x i32> %b, i64 3 + ; CHECK-DAG: %[[c0:.+]] = extractelement <4 x i32> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <4 x i32> %c, i64 1 + ; CHECK-DAG: %[[c2:.+]] = extractelement <4 x i32> %c, i64 2 + ; CHECK-DAG: %[[c3:.+]] = extractelement <4 x i32> %c, i64 3 + ; CHECK-DAG: %[[max0:.+]] = call i32 @dx.op.binary.i32(i32 39, i32 %[[a0]], i32 %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call i32 @dx.op.binary.i32(i32 39, i32 %[[a1]], i32 %[[b1]]) + ; CHECK-DAG: %[[max2:.+]] = call i32 @dx.op.binary.i32(i32 39, i32 %[[a2]], i32 %[[b2]]) + ; CHECK-DAG: %[[max3:.+]] = call i32 @dx.op.binary.i32(i32 39, i32 %[[a3]], i32 %[[b3]]) + ; CHECK-DAG: %[[min0:.+]] = call i32 @dx.op.binary.i32(i32 40, i32 %[[max0]], i32 %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call i32 @dx.op.binary.i32(i32 40, i32 %[[max1]], i32 %[[c1]]) + ; CHECK-DAG: %[[min2:.+]] = call i32 @dx.op.binary.i32(i32 40, i32 %[[max2]], i32 %[[c2]]) + ; CHECK-DAG: %[[min3:.+]] = call i32 @dx.op.binary.i32(i32 40, i32 %[[max3]], i32 %[[c3]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <4 x i32> poison, i32 %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <4 x i32> %[[ret0]], i32 %[[min1]], i64 1 + ; CHECK-DAG: %[[ret2:.+]] = insertelement <4 x i32> %[[ret1]], i32 %[[min2]], i64 2 + ; CHECK-DAG: %[[ret3:.+]] = insertelement <4 x i32> %[[ret2]], i32 %[[min3]], i64 3 + ; CHECK: ret <4 x i32> %[[ret3]] + %dx.clamp = call <4 x i32> @llvm.dx.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %dx.clamp +} + +; CHECK-LABEL: clamp_uint64_t4 +define noundef <2 x i64> @clamp_uint64_t4(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) { +entry: + ; CHECK-DAG: %[[a0:.+]] = extractelement <2 x i64> %a, i64 0 + ; CHECK-DAG: %[[a1:.+]] = extractelement <2 x i64> %a, i64 1 + ; CHECK-DAG: %[[b0:.+]] = extractelement <2 x i64> %b, i64 0 + ; CHECK-DAG: %[[b1:.+]] = extractelement <2 x i64> %b, i64 1 + ; CHECK-DAG: %[[c0:.+]] = extractelement <2 x i64> %c, i64 0 + ; CHECK-DAG: %[[c1:.+]] = extractelement <2 x i64> %c, i64 1 + ; CHECK-DAG: %[[max0:.+]] = call i64 @dx.op.binary.i64(i32 39, i64 %[[a0]], i64 %[[b0]]) + ; CHECK-DAG: %[[max1:.+]] = call i64 @dx.op.binary.i64(i32 39, i64 %[[a1]], i64 %[[b1]]) + ; CHECK-DAG: %[[min0:.+]] = call i64 @dx.op.binary.i64(i32 40, i64 %[[max0]], i64 %[[c0]]) + ; CHECK-DAG: %[[min1:.+]] = call i64 @dx.op.binary.i64(i32 40, i64 %[[max1]], i64 %[[c1]]) + ; CHECK-DAG: %[[ret0:.+]] = insertelement <2 x i64> poison, i64 %[[min0]], i64 0 + ; CHECK-DAG: %[[ret1:.+]] = insertelement <2 x i64> %[[ret0]], i64 %[[min1]], i64 1 + ; CHECK: ret <2 x i64> %[[ret1]] + %dx.clamp = call <2 x i64> @llvm.dx.uclamp.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) + ret <2 x i64> %dx.clamp +} + + +declare <3 x half> @llvm.dx.nclamp.v3f16(<3 x half>, <3 x half>, <3 x half>) +declare <4 x float> @llvm.dx.nclamp.v4f32(<4 x float>, <4 x float>, <4 x float>) +declare <2 x double> @llvm.dx.nclamp.v2f64(<2 x double>, <2 x double>, <2 x double>) +declare <4 x i32> @llvm.dx.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <3 x i16> @llvm.dx.uclamp.v3i32(<3 x i16>, <3 x i32>, <3 x i16>) +declare <4 x i32> @llvm.dx.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.dx.uclamp.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) + diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll new file mode 100644 index 00000000000000..7ad786f78974ca --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll @@ -0,0 +1,239 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "GLSL.std.450" + +; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 +; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 + +; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64 +; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 +; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 + +; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4 +; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4 +; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4 + +; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4 +; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4 +; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4 + +; CHECK-LABEL: Begin function test_sclamp_i16 +define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) { +entry: + ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] SClamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]] + %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c) + ret i16 %0 +} + +; CHECK-LABEL: Begin function test_sclamp_i32 +define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) { +entry: + ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] SClamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]] + %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c) + ret i32 %0 +} + +; CHECK-LABEL: Begin function test_sclamp_i64 +define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +entry: + ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] SClamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]] + %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c) + ret i64 %0 +} + +; CHECK-LABEL: Begin function test_nclamp_half +define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half noundef %c) { +entry: + ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] NClamp %[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]] + %0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c) + ret half %0 +} + +; CHECK-LABEL: Begin function test_nclamp_float +define noundef float @test_nclamp_float(float noundef %a, float noundef %b, float noundef %c) { +entry: + ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] NClamp %[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]] + %0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c) + ret float %0 +} + +; CHECK-LABEL: Begin function test_nclamp_double +define noundef double @test_nclamp_double(double noundef %a, double noundef %b, double noundef %c) { +entry: + ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] NClamp %[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]] + %0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c) + ret double %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i16 +define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) { +entry: + ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] UClamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]] + %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c) + ret i16 %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i32 +define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) { +entry: + ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] UClamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]] + %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c) + ret i32 %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i64 +define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +entry: + ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] UClamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]] + %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c) + ret i64 %0 +} + +; CHECK-LABEL: Begin function test_sclamp_v4i16 +define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) { +entry: + ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] SClamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]] + %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) + ret <4 x i16> %0 +} + +; CHECK-LABEL: Begin function test_sclamp_v4i32 +define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] SClamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]] + %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %0 +} + +; CHECK-LABEL: Begin function test_sclamp_v4i64 +define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) { +entry: + ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] SClamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]] + %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) + ret <4 x i64> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4half +define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) { +entry: + ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] NClamp %[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]] + %0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) + ret <4 x half> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4float +define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) { +entry: + ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] NClamp %[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]] + %0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) + ret <4 x float> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4double +define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 x double> noundef %b, <4 x double> noundef %c) { +entry: + ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] NClamp %[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]] + %0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c) + ret <4 x double> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i16 +define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) { +entry: + ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] UClamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]] + %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) + ret <4 x i16> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i32 +define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] UClamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]] + %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i64 +define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) { +entry: + ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] UClamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]] + %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) + ret <4 x i64> %0 +} + +declare half @llvm.spv.nclamp.f16(half, half, half) +declare float @llvm.spv.nclamp.f32(float, float, float) +declare double @llvm.spv.nclamp.f64(double, double, double) +declare i16 @llvm.spv.sclamp.i16(i16, i16, i16) +declare i32 @llvm.spv.sclamp.i32(i32, i32, i32) +declare i64 @llvm.spv.sclamp.i64(i64, i64, i64) +declare i16 @llvm.spv.uclamp.i16(i16, i16, i16) +declare i32 @llvm.spv.uclamp.i32(i32, i32, i32) +declare i64 @llvm.spv.uclamp.i64(i64, i64, i64) +declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>) +declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x float>) +declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x double>) +declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) +declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) +declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) +declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) + + diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp.ll b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll new file mode 100644 index 00000000000000..02e43b09a0a62b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll @@ -0,0 +1,242 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std" + +; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 +; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 + +; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64 +; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 +; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 + +; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4 +; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4 +; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4 + +; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4 +; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4 +; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4 + +; CHECK-LABEL: Begin function test_sclamp_i16 +define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) { +entry: + ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] s_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]] + %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c) + ret i16 %0 +} + +; CHECK-LABEL: Begin function test_sclamp_i32 +define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) { +entry: + ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] s_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]] + %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c) + ret i32 %0 +} + +; CHECK-LABEL: Begin function test_sclamp_i64 +define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +entry: + ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] s_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]] + %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c) + ret i64 %0 +} + +; CHECK-LABEL: Begin function test_nclamp_half +define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half noundef %c) { +entry: + ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]] + ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp %[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]] + %0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c) + ret half %0 +} + +; CHECK-LABEL: Begin function test_nclamp_float +define noundef float @test_nclamp_float(float noundef %a, float noundef %b, float noundef %c) { +entry: + ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]] + ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp %[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]] + %0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c) + ret float %0 +} + +; CHECK-LABEL: Begin function test_nclamp_double +define noundef double @test_nclamp_double(double noundef %a, double noundef %b, double noundef %c) { +entry: + ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]] + ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp %[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]] + %0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c) + ret double %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i16 +define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) { +entry: + ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] u_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]] + %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c) + ret i16 %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i32 +define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) { +entry: + ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] u_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]] + %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c) + ret i32 %0 +} + +; CHECK-LABEL: Begin function test_uclamp_i64 +define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +entry: + ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] u_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]] + %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c) + ret i64 %0 +} + +declare half @llvm.spv.nclamp.f16(half, half, half) +declare float @llvm.spv.nclamp.f32(float, float, float) +declare double @llvm.spv.nclamp.f64(double, double, double) +declare i16 @llvm.spv.sclamp.i16(i16, i16, i16) +declare i32 @llvm.spv.sclamp.i32(i32, i32, i32) +declare i64 @llvm.spv.sclamp.i64(i64, i64, i64) +declare i16 @llvm.spv.uclamp.i16(i16, i16, i16) +declare i32 @llvm.spv.uclamp.i32(i32, i32, i32) +declare i64 @llvm.spv.uclamp.i64(i64, i64, i64) + +; CHECK-LABEL: Begin function test_sclamp_v4i16 +define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) { +entry: + ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] s_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]] + %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) + ret <4 x i16> %0 +} + +; CHECK-LABEL: Begin function test_sclamp_v4i32 +define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] s_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]] + %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %0 +} + +; CHECK-LABEL: Begin function test_sclamp_v4i64 +define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) { +entry: + ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] s_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]] + %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) + ret <4 x i64> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4half +define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) { +entry: + ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp %[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]] + %0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) + ret <4 x half> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4float +define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) { +entry: + ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp %[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]] + %0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) + ret <4 x float> %0 +} + +; CHECK-LABEL: Begin function test_nclamp_v4double +define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 x double> noundef %b, <4 x double> noundef %c) { +entry: + ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp %[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]] + %0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c) + ret <4 x double> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i16 +define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) { +entry: + ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] u_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]] + %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) + ret <4 x i16> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i32 +define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) { +entry: + ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] u_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]] + %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) + ret <4 x i32> %0 +} + +; CHECK-LABEL: Begin function test_uclamp_v4i64 +define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) { +entry: + ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]] + ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] u_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]] + %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) + ret <4 x i64> %0 +} + +declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>) +declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x float>) +declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x double>) +declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) +declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) +declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) +declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) + + _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
