================
@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32<bit S, bits<2> sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, op, timm32_0_3, nxv4i1, nxv4f32>;
}
+multiclass sme2_fp8_fmopa_za32<string mnemonic, SDPatternOperator intrinsic> {
+ def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr<NAME, 1> {
+ bits<2> ZAda;
+ let Inst{1-0} = ZAda;
+ let Inst{2} = 0b0;
+
----------------
SpencerAbson wrote:
Since the intrinsic matches the pseudo-instruction, the machine-instruction
does not actually need to adopt the flags of the intrinsic
(`[IntrInaccessibleMemOnly, IntrHasSideEffects] => mayStore=1,mayLoad=1`).
This is probably a good thing, as the instructions do not actually access
memory and have their non-operand dependency on the FPMR described by `Uses`.
IMO, we should either be explicit about the effects of
`[IntrInaccessibleMemOnly, IntrHasSideEffects]` on the **pseudo-instruction**,
or disreguard this entirely. What do you think?
https://github.com/llvm/llvm-project/pull/118115
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