================
@@ -68,15 +66,18 @@ void test_builtin_elementwise_add_sat(float f1, float f2,
double d1, double d2,
long long int i2, si8 vi1, si8 vi2,
unsigned u1, unsigned u2, u4 vu1, u4 vu2,
_BitInt(31) bi1, _BitInt(31) bi2,
- unsigned _BitInt(55) bu1, unsigned
_BitInt(55) bu2) {
+ unsigned _BitInt(55) bu1, unsigned
_BitInt(55) bu2,
+ char c1, char c2, unsigned char uc1,
+ unsigned char uc2, short s1, short s2,
+ unsigned short us1, unsigned short us2) {
// CHECK: [[I1:%.+]] = load i64, ptr %i1.addr, align 8
// CHECK-NEXT: [[I2:%.+]] = load i64, ptr %i2.addr, align 8
// CHECK-NEXT: call i64 @llvm.sadd.sat.i64(i64 [[I1]], i64 [[I2]])
i1 = __builtin_elementwise_add_sat(i1, i2);
// CHECK: [[I1:%.+]] = load i64, ptr %i1.addr, align 8
// CHECK-NEXT: call i64 @llvm.sadd.sat.i64(i64 [[I1]], i64 10)
- i1 = __builtin_elementwise_add_sat(i1, 10);
+ i1 = __builtin_elementwise_add_sat(i1, (long long int)10);
----------------
frasercrmck wrote:
I've implemented a naive version of the RFC, but I'm not sure if we want to
require explicit casting of immediates in this case. It arguably matches the
vector behaviour, and floating-point behaviour, but it's still awkward.
Thoughts?
https://github.com/llvm/llvm-project/pull/119423
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