llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Mikołaj Piróg (mikolaj-pirog) <details> <summary>Changes</summary> Intel spec for avx10.2 (https://cdrdv2.intel.com/v1/dl/getContent/828965) has been updated. This PR changes relevant names from the "SATURATING CONVERT INSTRUCTIONS" chapter . --- Patch is 552.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123656.diff 20 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsX86.td (+24-24) - (modified) clang/lib/Headers/avx10_2_512convertintrin.h (+48-48) - (modified) clang/lib/Headers/avx10_2convertintrin.h (+96-96) - (modified) clang/test/CodeGen/X86/avx10_2_512convert-builtins.c (+24-24) - (modified) clang/test/CodeGen/X86/avx10_2convert-builtins.c (+48-48) - (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+24-24) - (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+12-12) - (modified) llvm/lib/Target/X86/X86ISelLowering.h (+12-12) - (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+21-21) - (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+12-12) - (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+49-49) - (modified) llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll (+136-136) - (modified) llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll (+272-272) - (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt (+416-416) - (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt (+416-416) - (modified) llvm/test/MC/X86/avx10.2convert-32-att.s (+416-416) - (modified) llvm/test/MC/X86/avx10.2convert-32-intel.s (+416-416) - (modified) llvm/test/MC/X86/avx10.2convert-64-att.s (+416-416) - (modified) llvm/test/MC/X86/avx10.2convert-64-intel.s (+416-416) - (modified) llvm/test/TableGen/x86-fold-tables.inc (+144-144) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index 18fc10eb85c027..001fc44890dd5c 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -5191,51 +5191,51 @@ let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] i } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtne2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; + def vcvt2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtne2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; + def vcvt2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtne2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; + def vcvt2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtne2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; + def vcvt2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtne2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; + def vcvt2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtne2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; + def vcvt2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtne2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; + def vcvt2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtne2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; + def vcvt2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtne2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; + def vcvt2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtne2ph2hf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; + def vcvt2ph2hf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtne2ph2hf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; + def vcvt2ph2hf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtne2ph2hf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; + def vcvt2ph2hf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { @@ -5251,51 +5251,51 @@ let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] i } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtneph2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; + def vcvtph2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtneph2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; + def vcvtph2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtneph2bf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; + def vcvtph2bf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtneph2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; + def vcvtph2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtneph2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; + def vcvtph2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtneph2bf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; + def vcvtph2bf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtneph2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; + def vcvtph2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtneph2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; + def vcvtph2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtneph2hf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; + def vcvtph2hf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { - def vcvtneph2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; + def vcvtph2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { - def vcvtneph2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; + def vcvtph2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { - def vcvtneph2hf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; + def vcvtph2hf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { diff --git a/clang/lib/Headers/avx10_2_512convertintrin.h b/clang/lib/Headers/avx10_2_512convertintrin.h index 60a5b1ef4548d8..2726a31dba36c1 100644 --- a/clang/lib/Headers/avx10_2_512convertintrin.h +++ b/clang/lib/Headers/avx10_2_512convertintrin.h @@ -138,78 +138,78 @@ _mm512_maskz_cvtbiassph_phf8(__mmask32 __U, __m512i __A, __m512h __B) { } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_cvtne2ph_pbf8(__m512h __A, __m512h __B) { - return (__m512i)__builtin_ia32_vcvtne2ph2bf8_512((__v32hf)(__A), +_mm512_cvt2ph_bf8(__m512h __A, __m512h __B) { + return (__m512i)__builtin_ia32_vcvt2ph2bf8_512((__v32hf)(__A), (__v32hf)(__B)); } -static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtne2ph_pbf8( +static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvt2ph_bf8( __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_pbf8(__A, __B), (__v64qi)__W); + (__mmask64)__U, (__v64qi)_mm512_cvt2ph_bf8(__A, __B), (__v64qi)__W); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtne2ph_pbf8(__mmask64 __U, __m512h __A, __m512h __B) { +_mm512_maskz_cvt2ph_bf8(__mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_pbf8(__A, __B), + (__mmask64)__U, (__v64qi)_mm512_cvt2ph_bf8(__A, __B), (__v64qi)(__m512i)_mm512_setzero_si512()); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_cvtnes2ph_pbf8(__m512h __A, __m512h __B) { - return (__m512i)__builtin_ia32_vcvtne2ph2bf8s_512((__v32hf)(__A), +_mm512_cvts2ph_bf8(__m512h __A, __m512h __B) { + return (__m512i)__builtin_ia32_vcvt2ph2bf8s_512((__v32hf)(__A), (__v32hf)(__B)); } -static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtnes2ph_pbf8( +static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvts2ph_bf8( __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_pbf8(__A, __B), (__v64qi)__W); + (__mmask64)__U, (__v64qi)_mm512_cvts2ph_bf8(__A, __B), (__v64qi)__W); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtnes2ph_pbf8(__mmask64 __U, __m512h __A, __m512h __B) { +_mm512_maskz_cvts2ph_bf8(__mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_pbf8(__A, __B), + (__mmask64)__U, (__v64qi)_mm512_cvts2ph_bf8(__A, __B), (__v64qi)(__m512i)_mm512_setzero_si512()); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_cvtne2ph_phf8(__m512h __A, __m512h __B) { - return (__m512i)__builtin_ia32_vcvtne2ph2hf8_512((__v32hf)(__A), +_mm512_cvt2ph_hf8(__m512h __A, __m512h __B) { + return (__m512i)__builtin_ia32_vcvt2ph2hf8_512((__v32hf)(__A), (__v32hf)(__B)); } -static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtne2ph_phf8( +static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvt2ph_hf8( __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_phf8(__A, __B), (__v64qi)__W); + (__mmask64)__U, (__v64qi)_mm512_cvt2ph_hf8(__A, __B), (__v64qi)__W); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtne2ph_phf8(__mmask64 __U, __m512h __A, __m512h __B) { +_mm512_maskz_cvt2ph_hf8(__mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_phf8(__A, __B), + (__mmask64)__U, (__v64qi)_mm512_cvt2ph_hf8(__A, __B), (__v64qi)(__m512i)_mm512_setzero_si512()); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_cvtnes2ph_phf8(__m512h __A, __m512h __B) { - return (__m512i)__builtin_ia32_vcvtne2ph2hf8s_512((__v32hf)(__A), +_mm512_cvts2ph_hf8(__m512h __A, __m512h __B) { + return (__m512i)__builtin_ia32_vcvt2ph2hf8s_512((__v32hf)(__A), (__v32hf)(__B)); } -static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtnes2ph_phf8( +static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvts2ph_hf8( __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_phf8(__A, __B), (__v64qi)__W); + (__mmask64)__U, (__v64qi)_mm512_cvts2ph_hf8(__A, __B), (__v64qi)__W); } static __inline__ __m512i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtnes2ph_phf8(__mmask64 __U, __m512h __A, __m512h __B) { +_mm512_maskz_cvts2ph_hf8(__mmask64 __U, __m512h __A, __m512h __B) { return (__m512i)__builtin_ia32_selectb_512( - (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_phf8(__A, __B), + (__mmask64)__U, (__v64qi)_mm512_cvts2ph_hf8(__A, __B), (__v64qi)(__m512i)_mm512_setzero_si512()); } @@ -232,74 +232,74 @@ _mm512_maskz_cvtnehf8_ph(__mmask32 __U, __m256i __A) { } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_cvtneph_pbf8(__m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask( +_mm512_cvtph_bf8(__m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_mask_cvtneph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask( +_mm512_mask_cvtph_bf8(__m256i __W, __mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtneph_pbf8(__mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask( +_mm512_maskz_cvtph_bf8(__mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_cvtnesph_pbf8(__m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask( +_mm512_cvtsph_bf8(__m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_mask_cvtnesph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask( +_mm512_mask_cvtsph_bf8(__m256i __W, __mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtnesph_pbf8(__mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask( +_mm512_maskz_cvtsph_bf8(__mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_cvtneph_phf8(__m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask( +_mm512_cvtph_hf8(__m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_mask_cvtneph_phf8(__m256i __W, __mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask( +_mm512_mask_cvtph_hf8(__m256i __W, __mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtneph_phf8(__mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask( +_mm512_maskz_cvtph_hf8(__mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_cvtnesph_phf8(__m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask( +_mm512_cvtsph_hf8(__m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_mask_cvtnesph_phf8(__m256i __W, __mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask( +_mm512_mask_cvtsph_hf8(__m256i __W, __mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U); } static __inline__ __m256i __DEFAULT_FN_ATTRS512 -_mm512_maskz_cvtnesph_phf8(__mmask32 __U, __m512h __A) { - return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask( +_mm512_maskz_cvtsph_hf8(__mmask32 __U, __m512h __A) { + return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask( (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U); } diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h index efe8477cbbf9be..cf52b466239518 100644 --- a/clang/lib/Headers/avx10_2convertintrin.h +++ b/clang/lib/Headers/avx10_2convertintrin.h @@ -233,155 +233,155 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) { (__mmask16)__U); } -static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A, +static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A, __m128h __B) { - return (__m128i)__builtin_ia32_vcvtne2ph2bf8_128((__v8hf)(__A), + return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A), (__v8hf)(__B)); } static __inline__ __m128i __DEFAULT_FN_ATTRS128 -_mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { +_mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( - (__mmask16)__U, (__v16qi)_mm_cvtne2ph_pbf8(__A, __B), (__v16qi)__W); + (__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B), (__v16qi)__W); } static __inline__ __m128i __DEFAULT_FN_ATTRS128 -_mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) { +_mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) { return (__m128i)__builtin_ia32_selectb_128( - (__mmask16)__U, (__v16qi)_mm_cvtne2ph_pbf8(__A, __B), + (__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B), (__v16qi)(__m128i)_mm_setzero_si128()); } static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) { - return (__m256i)__builtin_ia32_vcvtne2ph2bf8_256((__v16hf)(__A), +_mm256_cvt2ph_bf8(__m256h __A, __m256h __B) { + return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A), (__v16hf)(__B)); } -static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8( +static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8( __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( - (__mmask16)__U, (__v32qi)_mm256_cvtne2ph_pbf8(__A, __B), (__v32qi)__W); + (__mmask16)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B), (__v32qi)__W); } static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) { +_mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) { return (__m256i)__builtin_ia32_selectb_256( - (__mmask16)__U, (__v32qi)_mm256_cvtne2ph_pbf8(__A, __B), + (__mmask16)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B), (__v32qi)(__m256i)_mm256_setzero_si256()); } static __inline__ __m128i __DEFAULT_FN_ATTRS128 -_mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) { - return (__m128i)__builtin_ia32_v... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/123656 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits