================
@@ -0,0 +1,11 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only
-verify
+
+#include <riscv_vector.h>
+
+// expected-no-diagnostics
+
+__attribute__((target("arch=+zvl128b")))
+void test_zvk_features(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
----------------
wangpc-pp wrote:
What do we get if without this PR?
https://github.com/llvm/llvm-project/pull/141548
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