llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Jim Lin (tclin914) <details> <summary>Changes</summary> The Andes CPU is configurable with optional extensions. The minimal required extension set does not include `B` and `Zbc` extensions. So we decided to remove them. --- Full diff: https://github.com/llvm/llvm-project/pull/144022.diff 7 Files Affected: - (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c (-5) - (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c (-4) - (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c (-5) - (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c (-4) - (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c (-4) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (-8) - (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s (+1-1) ``````````diff diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c index d8b3848d84520..b63800d72144a 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c @@ -10,7 +10,6 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) -// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -19,10 +18,6 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) -// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) -// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) -// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) -// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c index a0a1c35911409..f16228d0188d5 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c @@ -10,7 +10,6 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) -// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -19,9 +18,6 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) -// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) -// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) -// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c index 3f933ecd8ac83..424c4afbbba44 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c @@ -10,7 +10,6 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) -// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -18,10 +17,6 @@ // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) -// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) -// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) -// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) -// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c index 6460d701411bc..c00cc60640f62 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c @@ -10,7 +10,6 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) -// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -18,9 +17,6 @@ // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) -// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) -// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) -// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c index 4d9c514b756e6..7dc1383c9666a 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c @@ -10,7 +10,6 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) -// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -19,9 +18,6 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) -// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) -// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) -// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index de6f0ecfce737..ea353a44fed41 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -703,8 +703,6 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, - FeatureStdExtZbc, FeatureVendorXAndesPerf]>; def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", @@ -718,8 +716,6 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, - FeatureStdExtZbc, FeatureVendorXAndesPerf]>; def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series", @@ -736,7 +732,6 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, FeatureVendorXAndesPerf]>; def ANDES_NX45 : RISCVProcessorModel<"andes-nx45", @@ -750,7 +745,6 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, FeatureVendorXAndesPerf]>; def ANDES_A45 : RISCVProcessorModel<"andes-a45", @@ -764,7 +758,6 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, FeatureVendorXAndesPerf]>; def ANDES_AX45 : RISCVProcessorModel<"andes-ax45", @@ -778,5 +771,4 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB, FeatureVendorXAndesPerf]>; diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s index f6dc6eef3f0ff..d90dce8c5c3fc 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s # Two ALUs without dependency can be dispatched in the same cycle. add a0, a0, a0 `````````` </details> https://github.com/llvm/llvm-project/pull/144022 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
