================
@@ -5025,6 +5025,11 @@ def msve_vector_bits_EQ : Joined<["-"],
"msve-vector-bits=">, Group<m_aarch64_Fe
Visibility<[ClangOption, FlangOption]>,
HelpText<"Specify the size in bits of an SVE vector register. Defaults to
the"
" vector length agnostic value of \"scalable\". (AArch64 only)">;
+
+def mcpa_codegen : Flag<["-"], "mcpa-codegen">,
----------------
rgwott wrote:
Done.
https://github.com/llvm/llvm-project/pull/105669
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