[clang] [CIR] Implement folder for VecSplatOp (PR #143771)

[Amr Hesham via cfe-commits]

https://github.com/AmrDeveloper updated 
https://github.com/llvm/llvm-project/pull/143771

>From 301cfa7c4325c50185b3b6e2665dab467078d9f4 Mon Sep 17 00:00:00 2001
From: AmrDeveloper <am...@programmer.net>
Date: Wed, 11 Jun 2025 20:50:26 +0200
Subject: [PATCH] [CIR] Implement folder for VecSplatOp

---
 .../CIR/Dialect/Transforms/CIRSimplify.cpp    | 30 +++++++++++++++++--
 .../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp |  4 +--
 clang/test/CIR/Transforms/vector-splat.cir    | 16 ++++++++++
 3 files changed, 45 insertions(+), 5 deletions(-)
 create mode 100644 clang/test/CIR/Transforms/vector-splat.cir

diff --git a/clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp 
b/clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
index 67ed4124f26cc..3b7f08c441405 100644
--- a/clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
+++ b/clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
@@ -260,6 +260,31 @@ struct SimplifySwitch : public OpRewritePattern<SwitchOp> {
   }
 };
 
+struct SimplifyVecSplat : public OpRewritePattern<VecSplatOp> {
+  using OpRewritePattern<VecSplatOp>::OpRewritePattern;
+  LogicalResult matchAndRewrite(VecSplatOp op,
+                                PatternRewriter &rewriter) const override {
+    mlir::Value splatValue = op.getValue();
+    auto constant =
+        mlir::dyn_cast_if_present<cir::ConstantOp>(splatValue.getDefiningOp());
+    if (!constant)
+      return mlir::failure();
+
+    auto value = constant.getValue();
+    if (!mlir::isa_and_nonnull<cir::IntAttr>(value) &&
+        !mlir::isa_and_nonnull<cir::FPAttr>(value))
+      return mlir::failure();
+
+    cir::VectorType resultType = op.getResult().getType();
+    SmallVector<mlir::Attribute, 16> elements(resultType.getSize(), value);
+    auto constVecAttr = cir::ConstVectorAttr::get(
+        resultType, mlir::ArrayAttr::get(getContext(), elements));
+
+    rewriter.replaceOpWithNewOp<cir::ConstantOp>(op, constVecAttr);
+    return mlir::success();
+  }
+};
+
 
//===----------------------------------------------------------------------===//
 // CIRSimplifyPass
 
//===----------------------------------------------------------------------===//
@@ -275,7 +300,8 @@ void populateMergeCleanupPatterns(RewritePatternSet 
&patterns) {
   patterns.add<
     SimplifyTernary,
     SimplifySelect,
-    SimplifySwitch
+    SimplifySwitch,
+    SimplifyVecSplat
   >(patterns.getContext());
   // clang-format on
 }
@@ -288,7 +314,7 @@ void CIRSimplifyPass::runOnOperation() {
   // Collect operations to apply patterns.
   llvm::SmallVector<Operation *, 16> ops;
   getOperation()->walk([&](Operation *op) {
-    if (isa<TernaryOp, SelectOp, SwitchOp>(op))
+    if (isa<TernaryOp, SelectOp, SwitchOp, VecSplatOp>(op))
       ops.push_back(op);
   });
 
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp 
b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index a96501ab2c384..bd4ef3e76d7d3 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -936,9 +936,7 @@ mlir::LogicalResult 
CIRToLLVMConstantOpLowering::matchAndRewrite(
     }
 
     attr = rewriter.getArrayAttr(components);
-  }
-
-  else {
+  } else {
     return op.emitError() << "unsupported constant type " << op.getType();
   }
 
diff --git a/clang/test/CIR/Transforms/vector-splat.cir 
b/clang/test/CIR/Transforms/vector-splat.cir
new file mode 100644
index 0000000000000..e2274b8627b17
--- /dev/null
+++ b/clang/test/CIR/Transforms/vector-splat.cir
@@ -0,0 +1,16 @@
+// RUN: cir-opt %s -cir-simplify -o - | FileCheck %s
+
+!s32i = !cir.int<s, 32>
+
+module  {
+  cir.func @fold_shuffle_vector_op_test() -> !cir.vector<4 x !s32i> {
+    %v = cir.const #cir.int<3> : !s32i
+    %vec = cir.vec.splat %v : !s32i, !cir.vector<4 x !s32i>
+    cir.return %vec : !cir.vector<4 x !s32i>
+  }
+
+  // CHECK: cir.func @fold_shuffle_vector_op_test() -> !cir.vector<4 x !s32i> {
+  // CHECK-NEXT: %0 = cir.const #cir.const_vector<[#cir.int<3> : !s32i, 
#cir.int<3> : !s32i,
+  // CHECK-SAME: #cir.int<3> : !s32i, #cir.int<3> : !s32i]> : !cir.vector<4 x 
!s32i>
+  // CHECK-NEXT: cir.return %0 : !cir.vector<4 x !s32i>
+}

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