llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) <details> <summary>Changes</summary> These extensions were ratified in June 2024. --- Patch is 27.74 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/157015.diff 23 Files Affected: - (modified) clang/test/CodeGen/RISCV/attr-hw-shadow-stack.c (+4-4) - (modified) clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c (+2-2) - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+2-2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4-4) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/calls.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/jumptable-swguarded.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/lpad.ll (+4-4) - (modified) llvm/test/CodeGen/RISCV/nest-register.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/shadowcallstack.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/tail-calls.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll (+1-1) - (modified) llvm/test/MC/RISCV/attribute-arch-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/compressed-zicfiss.s (+6-6) - (modified) llvm/test/MC/RISCV/option-arch.s (+1-1) - (modified) llvm/test/MC/RISCV/tail-call.s (+4-4) - (modified) llvm/test/MC/RISCV/zicfilp-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/zicfilp-valid.s (+6-6) - (modified) llvm/test/MC/RISCV/zicfiss-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/zicfiss-valid.s (+6-6) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+8-8) ``````````diff diff --git a/clang/test/CodeGen/RISCV/attr-hw-shadow-stack.c b/clang/test/CodeGen/RISCV/attr-hw-shadow-stack.c index cabff7e598eb0..1a7671d16f342 100644 --- a/clang/test/CodeGen/RISCV/attr-hw-shadow-stack.c +++ b/clang/test/CodeGen/RISCV/attr-hw-shadow-stack.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zicfiss -emit-llvm -o - %s -fcf-protection=return | FileCheck %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zicfiss -emit-llvm -o - %s | FileCheck -check-prefix=NOSHADOWSTACK %s -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zicfiss -emit-llvm -o - %s -fcf-protection=return | FileCheck %s -// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zicfiss -emit-llvm -o - %s | FileCheck -check-prefix=NOSHADOWSTACK %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +zicfiss -emit-llvm -o - %s -fcf-protection=return | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +zicfiss -emit-llvm -o - %s | FileCheck -check-prefix=NOSHADOWSTACK %s +// RUN: %clang_cc1 -triple riscv32 -target-feature +zicfiss -emit-llvm -o - %s -fcf-protection=return | FileCheck %s +// RUN: %clang_cc1 -triple riscv32 -target-feature +zicfiss -emit-llvm -o - %s | FileCheck -check-prefix=NOSHADOWSTACK %s int foo(int *a) { return *a; } diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c index aa038a18693e0..f488347ee35b8 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c @@ -17,6 +17,8 @@ // CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) // CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) // CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) +// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) // CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) @@ -65,7 +67,5 @@ // CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions -// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) -// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-EMPTY: // CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicfilp1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_xsifivecdiscarddlone1p0_xsifivecflushdlone1p0 diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 413275dba8438..cbffa0aed6e1d 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -24,6 +24,8 @@ // CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) // CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores) // CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) +// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) // CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) @@ -212,8 +214,6 @@ // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-NEXT: p 0.15 'P' ('Base P' (Packed SIMD)) -// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) -// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bf5dca481cd2b..f34fa7d782cb6 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -165,8 +165,8 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, "'Zimop' (May-Be-Operations)">; def FeatureStdExtZicfilp - : RISCVExperimentalExtension<1, 0, "Landing pad", - [FeatureStdExtZicsr]>; + : RISCVExtension<1, 0, "Landing pad", + [FeatureStdExtZicsr]>; def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, AssemblerPredicate<(all_of FeatureStdExtZicfilp), "'Zicfilp' (Landing pad)">; @@ -174,8 +174,8 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">, AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>; def FeatureStdExtZicfiss - : RISCVExperimentalExtension<1, 0, "Shadow stack", - [FeatureStdExtZicsr, FeatureStdExtZimop]>; + : RISCVExtension<1, 0, "Shadow stack", + [FeatureStdExtZicsr, FeatureStdExtZimop]>; def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, AssemblerPredicate<(all_of FeatureStdExtZicfiss), "'Zicfiss' (Shadow stack)">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index eacd5c9a88bba..3e97358f6c667 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -132,7 +132,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s ; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s +; RUN: llc -mtriple=riscv32 -mattr=+zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s ; RUN: llc -mtriple=riscv32 -mattr=+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV32ZVBC32E %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV32ZVKGS %s @@ -278,7 +278,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s ; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s +; RUN: llc -mtriple=riscv64 -mattr=+zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s ; RUN: llc -mtriple=riscv64 -mattr=+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV64ZVKGS %s diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll index f30c453d7f6bc..589f1192b6ec8 100644 --- a/llvm/test/CodeGen/RISCV/calls.ll +++ b/llvm/test/CodeGen/RISCV/calls.ll @@ -11,7 +11,7 @@ ; RUN: | FileCheck -check-prefix=RV64I-MEDIUM %s ; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-LARGE %s -; RUN: llc -code-model=large -mtriple=riscv64 -mattr=experimental-zicfilp -verify-machineinstrs < %s \ +; RUN: llc -code-model=large -mtriple=riscv64 -mattr=zicfilp -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-LARGE-ZICFILP %s declare i32 @external_function(i32) diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 01b8c0eaadb05..85e6eb70db612 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -52,8 +52,6 @@ ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). ; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs). ; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions). -; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). -; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). @@ -276,6 +274,8 @@ ; CHECK-NEXT: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement). ; CHECK-NEXT: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores). ; CHECK-NEXT: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences). +; CHECK-NEXT: zicfilp - 'Zicfilp' (Landing pad). +; CHECK-NEXT: zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: zicntr - 'Zicntr' (Base Counters and Timers). ; CHECK-NEXT: zicond - 'Zicond' (Integer Conditional Operations). ; CHECK-NEXT: zicsr - 'Zicsr' (CSRs). diff --git a/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll b/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll index b4ab0585c0cc9..e2402f91f3d20 100644 --- a/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll +++ b/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+zicfilp < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+zicfilp < %s | FileCheck %s ; RUN: llc -mtriple riscv32 < %s | FileCheck %s --check-prefix=NO-ZICFILP ; RUN: llc -mtriple riscv64 < %s | FileCheck %s --check-prefix=NO-ZICFILP diff --git a/llvm/test/CodeGen/RISCV/lpad.ll b/llvm/test/CodeGen/RISCV/lpad.ll index 93eda6f10eedb..c94fc1be6353c 100644 --- a/llvm/test/CodeGen/RISCV/lpad.ll +++ b/llvm/test/CodeGen/RISCV/lpad.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp \ +; RUN: llc -mtriple riscv32 -mattr=+zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple riscv64 -mattr=+zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple riscv32 -mattr=+zicfilp \ ; RUN: -riscv-landing-pad-label=1 < %s | FileCheck %s --check-prefixes=FIXED-ONE,FIXED-ONE-RV32 -; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp \ +; RUN: llc -mtriple riscv64 -mattr=+zicfilp \ ; RUN: -riscv-landing-pad-label=1 < %s | FileCheck %s --check-prefixes=FIXED-ONE,FIXED-ONE-RV64 ; Check indirectbr. diff --git a/llvm/test/CodeGen/RISCV/nest-register.ll b/llvm/test/CodeGen/RISCV/nest-register.ll index 6e892e05c4297..73d3d772e14a8 100644 --- a/llvm/test/CodeGen/RISCV/nest-register.ll +++ b/llvm/test/CodeGen/RISCV/nest-register.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicfilp -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-ZICFILP %s -; RUN: not llc -mtriple=riscv64 -target-abi=lp64e -mattr=+experimental-zicfilp \ +; RUN: not llc -mtriple=riscv64 -target-abi=lp64e -mattr=+zicfilp \ ; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=LP64E-ZICFILP %s ; Tests that the 'nest' parameter attribute causes the relevant parameter to be diff --git a/llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll b/llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll index 8a338a855c863..7eaf0fe8e6ca3 100644 --- a/llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll +++ b/llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -O0 -mtriple=riscv64 -mattr=+experimental-zicfilp -verify-machineinstrs < %s \ +; RUN: llc -O0 -mtriple=riscv64 -mattr=+zicfilp -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64 %s -; RUN: llc -O0 -mtriple=riscv64-unknown-linux-gnu -mattr=+experimental-zicfilp -verify-machineinstrs < %s \ +; RUN: llc -O0 -mtriple=riscv64-unknown-linux-gnu -mattr=+zicfilp -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64-LINUX %s declare void @llvm.init.trampoline(ptr, ptr, ptr) diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll index 03acd9491fed8..406982de81570 100644 --- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll +++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll @@ -3,9 +3,9 @@ ; RUN: | FileCheck %s --check-prefix=RV32 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefix=RV64 -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicfiss < %s \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-ZICFISS -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicfiss < %s \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-ZICFISS define void @f1() shadowcallstack { diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll index 366b37ac5d472..09ac4da9d63b1 100644 --- a/llvm/test/CodeGen/RISCV/tail-calls.ll +++ b/llvm/test/CodeGen/RISCV/tail-calls.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32-unknown-linux-gnu -o - %s | FileCheck %s -; RUN: llc -mtriple riscv32-unknown-linux-gnu -mattr=experimental-zicfilp \ +; RUN: llc -mtriple riscv32-unknown-linux-gnu -mattr=zicfilp \ ; RUN: -code-model=large -o - %s \ ; RUN: | FileCheck %s -check-prefix=CHECK-LARGE-ZICFILP ; RUN: llc -mtriple riscv32-unknown-elf -o - %s | FileCheck %s diff --git a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll index bccd28ee7e2b3..b70c1bbf6dd7d 100644 --- a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll +++ b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 ; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -stop-after=finalize-isel < %s | FileCheck -check-prefixes=ZICFILP %s +; RUN: llc -mtriple=riscv64 -mattr=+zicfilp -stop-after=finalize-isel < %s | FileCheck -check-prefixes=ZICFILP %s @brind.arr = internal unnamed_addr constant [2 x ptr] [ptr blockaddress(@brind, %5), ptr blockaddress(@brind, %8)], align 8 @x = dso_local global i32 0, align 4 diff --git a/llvm/test/MC/RISCV/attribute-arch-invalid.s b/llvm/test/MC/RISCV/attribute-arch-invalid.s index 4ed8f6a027894..cb206d63d47aa 100644 --- a/llvm/test/MC/RISCV/attribute-arch-invalid.s +++ b/llvm/test/MC/RISCV/attribute-arch-invalid.s @@ -5,5 +5,5 @@ ## Version strings are required for experimental extensions -.attribute arch, "rv32izicfilp" -# CHECK: error: invalid arch name 'rv32izicfilp', experimental extension requires explicit version number `zicfilp` +.attribute arch, "rv32izalasr" +# CHECK: error: invalid arch name 'rv32izalasr', experimental extension requires explicit version number `zalasr` diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s index 7d387b257b7b4..b1106428bca46 100644 --- a/llvm/test/MC/RISCV/compressed-zicfiss.s +++ b/llvm/test/MC/RISCV/compressed-zicfiss.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicfiss,+zcmop -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicfiss,+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+zicfiss,+zcmop -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicfiss,+zcmop -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicfiss,+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+zicfiss,+zcmop -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ diff --git a/llvm/test/MC/RISCV/option-arch.s b/llvm/test/MC/RISCV/option-arch.s index 0367ef317e71a..92d165e640c6f 100644 --- a/llvm/test/MC/RISCV/option-arch.s +++ b/llvm/test/MC/RISCV/option-arch.s @@ -1,7 +1,7 @@ # RUN: llvm-mc -triple riscv32 -mattr=+experimental -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK %s # RUN: llvm-mc -triple riscv32 -mattr=+experimental -filetype=obj < %s \ -# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+m,+a,+f,+zba,+experimental-zicfiss -d -M no-aliases - \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+m,+a,+f,+zba,+zicfiss -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-INST %s # Test '.option arch, +' and '.option arch, -' directive diff --git a/llvm/test/MC/RISCV/tail-call.s b/llvm/test/MC/RISCV/tail-call.s index 1c55bf5223caa..7b1f124d56ac0 100644 --- a/llvm/test/MC/RISCV/tail-call.s +++ b/llvm/test/MC/RISCV/tail-call.s @@ -8,14 +8,14 @@ # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s -# RUN: llvm-mc -file... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/157015 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
