================
@@ -6266,26 +6266,6 @@ SDValue
AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::aarch64_sve_clz:
return DAG.getNode(AArch64ISD::CTLZ_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
- case Intrinsic::aarch64_sme_cntsb:
- return DAG.getNode(AArch64ISD::RDSVL, DL, Op.getValueType(),
- DAG.getConstant(1, DL, MVT::i32));
- case Intrinsic::aarch64_sme_cntsh: {
- SDValue One = DAG.getConstant(1, DL, MVT::i32);
- SDValue Bytes = DAG.getNode(AArch64ISD::RDSVL, DL, Op.getValueType(), One);
- return DAG.getNode(ISD::SRL, DL, Op.getValueType(), Bytes, One);
- }
- case Intrinsic::aarch64_sme_cntsw: {
- SDValue Bytes = DAG.getNode(AArch64ISD::RDSVL, DL, Op.getValueType(),
- DAG.getConstant(1, DL, MVT::i32));
- return DAG.getNode(ISD::SRL, DL, Op.getValueType(), Bytes,
- DAG.getConstant(2, DL, MVT::i32));
- }
- case Intrinsic::aarch64_sme_cntsd: {
- SDValue Bytes = DAG.getNode(AArch64ISD::RDSVL, DL, Op.getValueType(),
- DAG.getConstant(1, DL, MVT::i32));
- return DAG.getNode(ISD::SRL, DL, Op.getValueType(), Bytes,
- DAG.getConstant(3, DL, MVT::i32));
- }
----------------
kmclaughlin-arm wrote:
I've added lowering for cntsd back into `LowerINTRINSIC_WO_CHAIN` and removed
most of the patterns.
As we discussed, further changes are needed to improve codegen for `cntsd * N`
where `N` is not a power of 2 which I will address separately. This is also the
reason I've changed some of the tests in sme-intrinsics-rdsvl.ll.
https://github.com/llvm/llvm-project/pull/154761
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