================
@@ -3744,6 +3751,89 @@ bool 
SPIRVInstructionSelector::selectResourceNonUniformIndex(
   return true;
 }
 
+bool SPIRVInstructionSelector::selectF16ToF32(Register ResVReg,
+                                              const SPIRVType *ResType,
+                                              MachineInstr &I) const {
+  assert(I.getNumOperands() == 3);
+  assert(I.getOperand(0).isReg());
+  assert(I.getOperand(2).isReg());
+  Register SrcReg = I.getOperand(2).getReg();
+  const SPIRVType *SrcRegType = GR.getSPIRVTypeForVReg(SrcReg);
+  LLT SrcType = MRI->getType(SrcReg);
+  SPIRVType *SrcEltType = GR.getScalarOrVectorComponentType(SrcRegType);
+  SPIRVType *ResEltType = GR.getScalarOrVectorComponentType(ResType);
+  const TargetRegisterClass *SrcRegClass = GR.getRegClass(SrcEltType);
+  const TargetRegisterClass *ResRegClass = GR.getRegClass(ResEltType);
+  MachineIRBuilder MIRBuilder(I);
+  const SPIRVType *Vec2ResType =
+      GR.getOrCreateSPIRVVectorType(ResEltType, 2, MIRBuilder, false);
+  const TargetRegisterClass *Vec2RegClass = GR.getRegClass(Vec2ResType);
+
+  bool Result = true;
+  MachineBasicBlock &BB = *I.getParent();
+  if (SrcType.isVector()) {
+    // We have a vector of uints to convert elementwise
+    uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
+    SmallVector<Register> ComponentRegisters;
+    for (uint64_t Idx = 0; Idx < ResultSize; Idx++) {
+      Register EltReg = MRI->createVirtualRegister(SrcRegClass);
+      Register FReg = MRI->createVirtualRegister(ResRegClass);
+      Register Vec2Reg = MRI->createVirtualRegister(Vec2RegClass);
+
+      Result =
+          BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
+              .addDef(EltReg)
+              .addUse(GR.getSPIRVTypeID(SrcEltType))
+              .addUse(SrcReg)
+              .addImm(Idx)
+              .constrainAllUses(TII, TRI, RBI);
+
+      Result &=
+          BuildMI(*I.getParent(), I, I.getDebugLoc(), 
TII.get(SPIRV::OpExtInst))
+              .addDef(Vec2Reg)
+              .addUse(GR.getSPIRVTypeID(Vec2ResType))
+              .addImm(
+                  static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
+              .addImm(GL::UnpackHalf2x16)
----------------
tcorringham wrote:

I have replaced the spv_legacyf16tof32 with spv_unpackhalf2x16 and moved the 
expansion of vector cases to clang codegen, where the expansion can be done 
more concisely.

https://github.com/llvm/llvm-project/pull/165860
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