https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/162986

>From 2dc5e8e616c061be15006d075d8115c14185834e Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <[email protected]>
Date: Sat, 11 Oct 2025 17:32:34 +0800
Subject: [PATCH 1/5] [RISCV] Set
 __GCC_CONSTRUCTIVE_SIZE/__GCC_DESTRUCTIVE_SIZE to 64 for riscv64

These two macros were added in https://github.com/llvm/llvm-project/pull/89446.

But the values may not be reasonable for RV64 systems because most
of them have a cache line size 64B.
---
 clang/lib/Basic/Targets/RISCV.h      | 12 ++++++++----
 clang/test/Preprocessor/init-riscv.c | 12 ++++++++++++
 2 files changed, 20 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/Preprocessor/init-riscv.c

diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 85fa4cc07dccf..6fc2cfb6c649d 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -125,10 +125,6 @@ class RISCVTargetInfo : public TargetInfo {
   ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
   llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
 
-  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
-    return std::make_pair(32, 32);
-  }
-
   bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
   bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
   bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
@@ -178,6 +174,10 @@ class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public 
RISCVTargetInfo {
     resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }
 
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    return std::make_pair(32, 32);
+  }
+
   bool setABI(const std::string &Name) override {
     if (Name == "ilp32e") {
       ABI = Name;
@@ -209,6 +209,10 @@ class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public 
RISCVTargetInfo {
     resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
   }
 
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    return std::make_pair(64, 64);
+  }
+
   bool setABI(const std::string &Name) override {
     if (Name == "lp64e") {
       ABI = Name;
diff --git a/clang/test/Preprocessor/init-riscv.c 
b/clang/test/Preprocessor/init-riscv.c
new file mode 100644
index 0000000000000..36b2b5a06b8c6
--- /dev/null
+++ b/clang/test/Preprocessor/init-riscv.c
@@ -0,0 +1,12 @@
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang_cc1 -E -dM -triple=riscv32 < /dev/null | \
+// RUN:     FileCheck -match-full-lines -check-prefixes=RV32 %s
+// RUN: %clang_cc1 -E -dM -triple=riscv64 < /dev/null | \
+// RUN:     FileCheck -match-full-lines -check-prefixes=RV64 %s
+
+// RV32: #define __GCC_CONSTRUCTIVE_SIZE 32
+// RV32: #define __GCC_DESTRUCTIVE_SIZE 32
+
+// RV64: #define __GCC_CONSTRUCTIVE_SIZE 64
+// RV64: #define __GCC_DESTRUCTIVE_SIZE 64
\ No newline at end of file

>From e0f0733cccf75975cb5bd260d5b73e3a71c3d1dc Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <[email protected]>
Date: Sat, 11 Oct 2025 17:41:23 +0800
Subject: [PATCH 2/5] Add new line at the EOF

---
 clang/test/Preprocessor/init-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Preprocessor/init-riscv.c 
b/clang/test/Preprocessor/init-riscv.c
index 36b2b5a06b8c6..b145ec4dad8d8 100644
--- a/clang/test/Preprocessor/init-riscv.c
+++ b/clang/test/Preprocessor/init-riscv.c
@@ -9,4 +9,4 @@
 // RV32: #define __GCC_DESTRUCTIVE_SIZE 32
 
 // RV64: #define __GCC_CONSTRUCTIVE_SIZE 64
-// RV64: #define __GCC_DESTRUCTIVE_SIZE 64
\ No newline at end of file
+// RV64: #define __GCC_DESTRUCTIVE_SIZE 64

>From d233bbdd8667b7a56ecaa265b16f02ada81eb0e3 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <[email protected]>
Date: Thu, 6 Nov 2025 16:21:08 +0800
Subject: [PATCH 3/5] Change to 64 for RV32/RV64

---
 clang/lib/Basic/Targets/RISCV.h      | 12 ++++--------
 clang/test/Preprocessor/init-riscv.c |  4 ++--
 2 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 6fc2cfb6c649d..21555b94fe65d 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -125,6 +125,10 @@ class RISCVTargetInfo : public TargetInfo {
   ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
   llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override;
 
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    return std::make_pair(64, 64);
+  }
+
   bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
   bool supportsCpuIs() const override { return getTriple().isOSLinux(); }
   bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
@@ -174,10 +178,6 @@ class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public 
RISCVTargetInfo {
     resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }
 
-  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
-    return std::make_pair(32, 32);
-  }
-
   bool setABI(const std::string &Name) override {
     if (Name == "ilp32e") {
       ABI = Name;
@@ -209,10 +209,6 @@ class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public 
RISCVTargetInfo {
     resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
   }
 
-  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
-    return std::make_pair(64, 64);
-  }
-
   bool setABI(const std::string &Name) override {
     if (Name == "lp64e") {
       ABI = Name;
diff --git a/clang/test/Preprocessor/init-riscv.c 
b/clang/test/Preprocessor/init-riscv.c
index b145ec4dad8d8..b91fddb06a22a 100644
--- a/clang/test/Preprocessor/init-riscv.c
+++ b/clang/test/Preprocessor/init-riscv.c
@@ -5,8 +5,8 @@
 // RUN: %clang_cc1 -E -dM -triple=riscv64 < /dev/null | \
 // RUN:     FileCheck -match-full-lines -check-prefixes=RV64 %s
 
-// RV32: #define __GCC_CONSTRUCTIVE_SIZE 32
-// RV32: #define __GCC_DESTRUCTIVE_SIZE 32
+// RV32: #define __GCC_CONSTRUCTIVE_SIZE 64
+// RV32: #define __GCC_DESTRUCTIVE_SIZE 64
 
 // RV64: #define __GCC_CONSTRUCTIVE_SIZE 64
 // RV64: #define __GCC_DESTRUCTIVE_SIZE 64

>From a62882a35ab42dfb1d192bb941894c9f22d476fd Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <[email protected]>
Date: Fri, 7 Nov 2025 11:13:36 +0800
Subject: [PATCH 4/5] Add ReleaseNotes

---
 clang/docs/ReleaseNotes.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ae21c69b2d3c5..390296c2e9496 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -580,6 +580,8 @@ RISC-V Support
 - Add `-march=unset` to clear any previous `-march=` value. This ISA string 
will
   be computed from `-mcpu` or the platform default.
 
+- `__GCC_CONSTRUCTIVE_SIZE` and `__GCC_DESTRUCTIVE_SIZE` are changed to 64.
+
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 

>From e1a5a16648635c21108b6e2db01150a335b1bcf0 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <[email protected]>
Date: Sat, 8 Nov 2025 15:06:15 +0800
Subject: [PATCH 5/5] Add clang links and remove riscv-registered-target

---
 clang/docs/ReleaseNotes.rst          | 3 ++-
 clang/test/Preprocessor/init-riscv.c | 2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 390296c2e9496..1870120325eaf 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -580,7 +580,8 @@ RISC-V Support
 - Add `-march=unset` to clear any previous `-march=` value. This ISA string 
will
   be computed from `-mcpu` or the platform default.
 
-- `__GCC_CONSTRUCTIVE_SIZE` and `__GCC_DESTRUCTIVE_SIZE` are changed to 64.
+- `__GCC_CONSTRUCTIVE_SIZE` and `__GCC_DESTRUCTIVE_SIZE` are changed to 64. 
These values are
+  unstable according to `Clang's documentation 
<https://clang.llvm.org/docs/LanguageExtensions.html#gcc-destructive-size-and-gcc-constructive-size>`_.
 
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/test/Preprocessor/init-riscv.c 
b/clang/test/Preprocessor/init-riscv.c
index b91fddb06a22a..4eeecccff4378 100644
--- a/clang/test/Preprocessor/init-riscv.c
+++ b/clang/test/Preprocessor/init-riscv.c
@@ -1,5 +1,3 @@
-// REQUIRES: riscv-registered-target
-
 // RUN: %clang_cc1 -E -dM -triple=riscv32 < /dev/null | \
 // RUN:     FileCheck -match-full-lines -check-prefixes=RV32 %s
 // RUN: %clang_cc1 -E -dM -triple=riscv64 < /dev/null | \

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