https://github.com/trdthg updated https://github.com/llvm/llvm-project/pull/132321
>From 211601e57174680b514f0123340000c288477d53 Mon Sep 17 00:00:00 2001 From: Mingzhu Yan <[email protected]> Date: Thu, 27 Nov 2025 06:39:54 +0000 Subject: [PATCH] [RISCV] Add Svrsw60t59b extension --- clang/test/Driver/print-supported-extensions-riscv.c | 1 + clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++ llvm/docs/RISCVUsage.rst | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++++-- llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 6 ++++++ llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 8 files changed, 29 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 681c912bd1612..56e34f2f312cb 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -159,6 +159,7 @@ // CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) // CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-NEXT: svrsw60t59b 1.0 'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59) // CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid) // CHECK-NEXT: xandesbfhcvt 5.0 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 56c738bc007fb..7003035a9478e 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -67,6 +67,7 @@ // CHECK-NOT: __riscv_svinval {{.*$}} // CHECK-NOT: __riscv_svnapot {{.*$}} // CHECK-NOT: __riscv_svpbmt {{.*$}} +// CHECK-NOT: __riscv_svrsw60t59b {{.*$}} // CHECK-NOT: __riscv_svvptc {{.*$}} // CHECK-NOT: __riscv_v {{.*$}} // CHECK-NOT: __riscv_v_elen {{.*$}} @@ -533,6 +534,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s // CHECK-SVVPTC-EXT: __riscv_svvptc 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isvrsw60t59b -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVRSW60T59B-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isvrsw60t59b -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVRSW60T59B-EXT %s +// CHECK-SVRSW60T59B-EXT: __riscv_svrsw60t59b 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32iv1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index a21f03d389444..02cfcb7eee791 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -165,6 +165,7 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt`` Supported + ``Svrsw60t59b`` Supported ``Svvptc`` Supported ``V`` Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bf1caafc2f9ba..166bccb4dfe5f 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1043,6 +1043,10 @@ def FeatureStdExtSvnapot def FeatureStdExtSvpbmt : RISCVExtension<1, 0, "Page-Based Memory Types">; +def FeatureStdExtSvrsw60t59b + : RISCVExtension<1, 0, + "PTE Reserved-for-Software Bits 60-59">; + def FeatureStdExtSvvptc : RISCVExtension<1, 0, "Obviating Memory-Management Instructions after Marking PTEs Valid">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index f26d4f09c92fb..c679984158585 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -65,11 +65,12 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svade %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADE %s ; RUN: llc -mtriple=riscv32 -mattr=+svadu %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADU %s ; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s +; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s +; RUN: llc -mtriple=riscv32 -mattr=+svrsw60t59b %s -o - | FileCheck --check-prefixes=CHECK,RV32SVRSW60T59B %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV32SVUKTE %s ; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s -; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck --check-prefix=RV32XCVELW %s @@ -218,9 +219,10 @@ ; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s +; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s +; RUN: llc -mtriple=riscv64 -mattr=+svrsw60t59b %s -o - | FileCheck --check-prefixes=CHECK,RV64SVRSW60T59B %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s ; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s -; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s ; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s ; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s @@ -385,6 +387,7 @@ ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" ; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3" ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" +; RV32SVRSW60T59B: .attribute 5, "rv32i2p1_svrsw60t59b1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0" ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0" @@ -538,6 +541,7 @@ ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" ; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3" ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" +; RV64SVRSW60T59B: .attribute 5, "rv64i2p1_svrsw60t59b1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0" ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 010d3c68b5ef1..9319643b4be6e 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -182,6 +182,7 @@ ; CHECK-NEXT: svinval - 'Svinval' (Fine-Grained Address-Translation Cache Invalidation). ; CHECK-NEXT: svnapot - 'Svnapot' (NAPOT Translation Contiguity). ; CHECK-NEXT: svpbmt - 'Svpbmt' (Page-Based Memory Types). +; CHECK-NEXT: svrsw60t59b - 'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59). ; CHECK-NEXT: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid). ; CHECK-NEXT: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. ; CHECK-NEXT: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores. diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index e41c9eac982a7..e43c40ba464b3 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -399,6 +399,12 @@ .attribute arch, "rv32i_svbare1p0" # CHECK: attribute 5, "rv32i2p1_svbare1p0" +.attribute arch, "rv32i_svrsw60t59b1p0" +# CHECK: attribute 5, "rv32i2p1_svrsw60t59b1p0" + +.attribute arch, "rv64i_svrsw60t59b1p0" +# CHECK: attribute 5, "rv64i2p1_svrsw60t59b1p0" + .attribute arch, "rv32i_svukte0p3" # CHECK: attribute 5, "rv32i2p1_svukte0p3" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c55cd94048cc5..2a4710fc9d0ce 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1136,6 +1136,7 @@ R"(All available -march extensions for RISC-V svinval 1.0 svnapot 1.0 svpbmt 1.0 + svrsw60t59b 1.0 svvptc 1.0 xandesbfhcvt 5.0 xandesperf 5.0 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
