https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/172135
>From 3e4c3c13eba70ff8b347bcc8c40cdb4ad0b80e75 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Fri, 12 Dec 2025 23:08:16 -0800 Subject: [PATCH 1/2] [llvm][RISCV] Add frm range check for xsfvfnrclipxfqf --- clang/lib/Sema/SemaRISCV.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index cfe30fdc73ba1..a5e9611c88795 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -1128,6 +1128,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm: return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu: @@ -1271,6 +1273,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tu: return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4); case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m: case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m: @@ -1440,6 +1444,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tum: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tumu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_mu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tum: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tumu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_mu: return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4); case RISCV::BI__builtin_riscv_ntl_load: case RISCV::BI__builtin_riscv_ntl_store: >From dc71b2caf1beae2b701b2730069481770cbc47f5 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Sun, 14 Dec 2025 21:09:35 -0800 Subject: [PATCH 2/2] fixup! group case --- clang/lib/Sema/SemaRISCV.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index a5e9611c88795..6153948a6a589 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -1100,6 +1100,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm: case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm: case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm: case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu: case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu: case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu: @@ -1128,8 +1130,6 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm: return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu: @@ -1207,6 +1207,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m: @@ -1273,8 +1275,6 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tu: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tu: return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4); case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m: case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m: @@ -1352,6 +1352,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum: case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum: case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tum: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu: @@ -1398,6 +1400,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tumu: + case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu: @@ -1444,11 +1448,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tum: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_tumu: case RISCVVector::BI__builtin_rvv_sf_vfnrclip_x_f_qf_rm_mu: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tum: - case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_tumu: case RISCVVector::BI__builtin_rvv_sf_vfnrclip_xu_f_qf_rm_mu: return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4); case RISCV::BI__builtin_riscv_ntl_load: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
