https://github.com/mgcarrasco created https://github.com/llvm/llvm-project/pull/173867
Commit 4c6f398 introduced a non-working compilation path for regular C/C++ to AMD SPIRV; this commit fixes it. For example, 4c6f398 was expecting an assembler phase but it was never supported since there is no assembler available for it. Thus, the compilation starting from source code failed. The compilation path is fixed by taking into account that we cannot rely on external dependencies such as `spirv-link` or `spirv-as`. Thus, the backend emits bitcode and the SPIRVAMDToolChain's linker takes care of generating the final SPIRV as we already do for HIP. >From 78dd3ba12c7d9bc20091c64179ae0c045fe7c603 Mon Sep 17 00:00:00 2001 From: Manuel Carrasco <[email protected]> Date: Mon, 29 Dec 2025 07:01:30 -0600 Subject: [PATCH] [Driver][SPIRV] Fix regular C/C++ compilation to AMD SPIRV. Commit 4c6f398 introduced a non-working compilation path for regular C/C++ to AMD SPIRV; this commit fixes it. For example, 4c6f398 was expecting an assembler phase but it was never supported since there is no assembler available for it. Thus, the compilation starting from source code failed. The compilation path is fixed by taking into account that we cannot rely on external dependencies such as spirv-link or spirv-as. Thus, the backend emits bitcode and the SPIRVAMDToolChain's linker takes care of generating the final SPIRV as we already do for HIP. --- clang/lib/Driver/Driver.cpp | 12 ++++++++++++ clang/test/Driver/spirv-amd-toolchain.c | 17 ++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 6a2ee1794b7d7..5dce2168236cf 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -5187,7 +5187,19 @@ Action *Driver::ConstructPhaseAction( offloadDeviceOnly() && !Args.hasFlag(options::OPT_fgpu_rdc, options::OPT_fno_gpu_rdc, false); + auto &DefaultToolChain = C.getDefaultToolChain(); + auto DefaultToolChainTriple = DefaultToolChain.getTriple(); + // For regular C/C++ to AMD SPIRV emit bitcode to avoid spirv-link + // dependency, SPIRVAMDToolChain's linker takes care of the generation of + // the final SPIRV. The only exception is -S without -emit-llvm to output + // textual SPIRV assembly, which fits the default compilation path. + bool EmitBitcodeForNonOffloadAMDSPIRV = + !OffloadingToolChain && DefaultToolChainTriple.isSPIRV() && + DefaultToolChainTriple.getVendor() == llvm::Triple::VendorType::AMD && + !(Args.hasArg(options::OPT_S) && !Args.hasArg(options::OPT_emit_llvm)); + if (Args.hasArg(options::OPT_emit_llvm) || + EmitBitcodeForNonOffloadAMDSPIRV || TargetDeviceOffloadKind == Action::OFK_SYCL || (((Input->getOffloadingToolChain() && Input->getOffloadingToolChain()->getTriple().isAMDGPU() && diff --git a/clang/test/Driver/spirv-amd-toolchain.c b/clang/test/Driver/spirv-amd-toolchain.c index 91cd43622518d..c9bba1e437e11 100644 --- a/clang/test/Driver/spirv-amd-toolchain.c +++ b/clang/test/Driver/spirv-amd-toolchain.c @@ -3,17 +3,28 @@ // PHASES: 0: input, "[[INPUT:.+]]", c // PHASES: 1: preprocessor, {0}, cpp-output // PHASES: 2: compiler, {1}, ir -// PHASES: 3: backend, {2}, assembler -// PHASES: 4: assembler, {3}, object -// PHASES: 5: linker, {4}, image +// PHASES: 3: backend, {2}, ir +// PHASES: 4: linker, {3}, image + +// RUN: %clang -### -ccc-print-phases -use-spirv-backend --target=spirv64-amd-amdhsa %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=PHASES // RUN: %clang -### -ccc-print-bindings --target=spirv64-amd-amdhsa %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=BINDINGS // BINDINGS: # "spirv64-amd-amdhsa" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[OUTPUT:.+]]" // BINDINGS: # "spirv64-amd-amdhsa" - "AMDGCN::Linker", inputs: ["[[OUTPUT]]"], output: "a.out" +// RUN: %clang -### -ccc-print-bindings -use-spirv-backend --target=spirv64-amd-amdhsa %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=BINDINGS + // RUN: %clang -### --target=spirv64-amd-amdhsa %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=INVOCATION // INVOCATION: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-disable-llvm-optzns" {{.*}} "-o" "[[OUTPUT:.+]]" "-x" "c" // INVOCATION: "{{.*}}llvm-link" "-o" "[[LINKED_OUTPUT:.+]]" "[[OUTPUT]]" // INVOCATION: "{{.*}}llvm-spirv" "--spirv-max-version=1.6" "--spirv-ext=+all" "--spirv-allow-unknown-intrinsics" "--spirv-lower-const-expr" "--spirv-preserve-auxdata" "--spirv-debug-info-version=nonsemantic-shader-200" "[[LINKED_OUTPUT]]" "-o" "a.out" + +// RUN: %clang -### -use-spirv-backend --target=spirv64-amd-amdhsa %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=INVOCATION-SPIRV-BACKEND +// INVOCATION-SPIRV-BACKEND: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-disable-llvm-optzns" {{.*}} "-o" "[[OUTPUT:.+]]" "-x" "c" +// INVOCATION-SPIRV-BACKEND: "{{.*}}llvm-link" "-o" "[[LINKED_OUTPUT:.+]]" "[[OUTPUT]]" +// INVOCATION-SPIRV-BACKEND: "-cc1" "-triple=spirv64-amd-amdhsa" "-emit-obj" {{.*}} "[[LINKED_OUTPUT]]" "-o" "a.out" _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
